Cryogenic Dielectric Etching for High-Aspect-Ratio Profiles

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Solution Overview

Problem

High aspect ratio etching of dielectrics in semiconductor devices faces challenges in achieving high etch selectivity, low sidewall etching, and straight profiles, particularly due to spontaneous chemical etching which compromises directionality, and existing methods require strong sidewall protection and trade-offs between etch rate and selectivity.

Innovation Solution

The method involves cooling the stack to cryogenic temperatures, using a leaner etch chemistry with reduced polymerizing components, and generating a plasma with specific etch gases like CF4, CHF3, and BCl3 to suppress chemical etching and enhance ion-induced etching, allowing for selective etching of dielectric layers with reduced lateral etching and increased etch rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching methods are used, then etching can proceed, but spontaneous chemical etching occurs which compromises directionality and results in poor sidewall profiles

Engineering Contradiction:
Improveetch directionality and sidewall profileVSAvoidspontaneous chemical etching
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent changes the temperature parameter to cryogenic conditions (below -20°C) to suppress spontaneous chemical etching reactions while maintaining ion-induced etching, thereby improving etch directionality and sidewall profile quality

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses a fluorocarbon-based plasma environment that creates a protective polymer coating on sidewalls, effectively creating an inert protective layer that prevents unwanted chemical reactions and maintains straight sidewall profiles

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

2Object-generated harmful factors

If strong sidewall protection is used, then sidewall etching is reduced, but etch selectivity and etch rate must be compromised

Engineering Contradiction:
Improvesidewall etchingVSAvoidetch rate and selectivity
Core Design Contradiction:
Object-generated harmful factorsVSProductivity

Solution Approach 1:

The patent changes the temperature parameter to cryogenic conditions, which allows the use of leaner etch chemistries with reduced polymerizing components, thereby achieving sidewall protection without sacrificing etch rate or selectivity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite approach combining cryogenic temperature control with specific fluorocarbon-based plasma chemistry to achieve both sidewall protection and high etch performance simultaneously

Inventive Principle:
Principle #40Composite materials

3Productivity

If high etch rate is achieved, then productivity improves, but selectivity to the mask decreases

Engineering Contradiction:
Improveetch rateVSAvoidmask selectivity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the temperature parameter to cryogenic conditions, which enables the use of leaner etch chemistries that maintain high etch rates while improving mask selectivity through reduced polymer deposition on the mask surface

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables high aspect ratio etching of dielectrics with improved selectivity and reduced bowing, striation, and tapering, while eliminating the need for strong sidewall protection, thus enhancing etch rate and contact shape quality.

Implementation Method 1

A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 2

enhance ion-induced etching

Methodology Applied
Scientific EffectIon-induced etching:

Implementation Method 3

The stack is cooled with a coolant with a coolant temperature below −20°0 C.

Methodology Applied
Scientific EffectCryogenic cooling: Cryogenics

Implementation Method 4

suppress chemical etching

Methodology Applied
Scientific EffectChemical etching suppression:

Data Source

PatentUS20240258128A1Plasma etching chemistries of high aspect ratio features in dielectrics
Publication Date: 2024.08.01 LAM RES CORP
  • US20240258128A1 patent drawing
  • US20240258128A1 patent drawing
  • US20240258128A1 patent drawing

AI summary

A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below −20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask.