Cryogenic Implantation for NMOS Transistor Dopant Activation
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Solution Overview
Problem
Integrated circuits face challenges in achieving high-speed operation for logic circuits and reducing leakage current in memory cells while maintaining fabrication costs, particularly in the formation of NMOS transistors.
Innovation Solution
Concurrently implanting source and drain regions of NMOS transistors at cryogenic temperatures with an amorphizing species and arsenic, followed by phosphorus implantation, with optional anneal processes to reduce crystal defects and enhance dopant activation, while maintaining separate implantation for PMOS transistors to control costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If concurrent cryogenic implantation is used for logic and memory NMOS transistors, then manufacturing precision and dopant activation are improved, but fabrication cost increases
Solution Approach 1:
The patent segments the implantation process into two distinct groups: logic NMOS transistors receive full concurrent cryogenic implantation with amorphizing species and phosphorus, while memory NMOS transistors receive only the amorphizing species implantation. This segmentation allows optimization of dopant activation for logic circuits without incurring the full cost of concurrent implantation for all transistor types, thereby resolving the contradiction between manufacturing precision and fabrication cost.
Solution Approach 2:
The patent applies local quality by providing different implantation treatments to different regions of the integrated circuit. Logic NMOS transistors, which require high-speed operation, receive enhanced phosphorus doping at cryogenic temperatures, while memory NMOS transistors receive standard doping. This localized differentiation optimizes performance where needed while controlling overall fabrication costs.
2Manufacturing precision
If amorphizing species is implanted at cryogenic temperature, then crystal defects are reduced, but process complexity increases
Solution Approach 1:
The patent applies preliminary action by first implanting the amorphizing species at cryogenic temperatures to create an amorphous layer, which is then followed by phosphorus implantation. This preliminary amorphization step prepares the crystal structure to accept dopants more effectively, reducing crystal defects. The use of a common implant mask for both logic and memory NMOS transistors during the amorphizing species implantation simplifies the overall process despite the cryogenic requirement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced crystal defects, improved dopant activation, and lower fabrication costs, enabling high-speed operation and reduced leakage current in NMOS transistors, thereby enhancing the performance and cost-effectiveness of integrated circuits.
Implementation Method 1
Source and drain regions of a logic NMOS transistor and a memory NMOS transistor are concurrently implanted at a cryogenic temperature with an amorphizing species followed by arsenic
Implementation Method 2
Source and drain regions of a logic NMOS transistor and a memory NMOS transistor are concurrently implanted at a cryogenic temperature with an amorphizing species
Implementation Method 3
The source and drain regions of the logic NMOS transistor are further implanted with phosphorus at a non-cryogenic temperature
Implementation Method 4
the memory NMOS transistor is covered by a mask which blocks the phosphorus
Data Source
AI summary
An integrated circuit includes logic circuits of NMOS and PMOS transistors, and memory cells with NMOS and PMOS transistors. A common NSD implant mask exposes source and drain regions of a logic NMOS transistor and a memory NMOS transistor. The source and drain regions of the logic NMOS transistor and the memory NMOS transistor are concurrently implanted at a cryogenic temperature with an amorphizing species followed by arsenic. Phosphorus is concurrently implanted in the source and drain regions of the logic NMOS transistor and the memory NMOS transistor. The source and drain regions of the logic NMOS transistor are further implanted with phosphorus at a non-cryogenic temperature while the memory NMOS transistor is covered by a mask which blocks the phosphorus.