Cryptographic NTT Accelerator With Pipelined Butterfly Circuits
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Solution Overview
Problem
Existing cryptographic systems face challenges in efficiently performing Number Theoretic Transform (NTT) computations due to increased circuitry area and memory access overhead in pipelined and parallel architectures, which are crucial for lattice-based cryptosystems to resist quantum computers.
Innovation Solution
A cryptographic accelerator combines pipelined and parallel butterfly operator circuits to perform NTT/INTT operations, utilizing registers to reduce memory access overhead and efficiently process polynomial coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pipelined architectures are used to accelerate NTT computations, then computational throughput is improved, but circuitry area increases due to data dependencies between NTT stages
Solution Approach 1:
The NTT computation is divided into multiple stages, with each stage processing a subset of the data. This segmentation allows the use of smaller, more manageable circuitry blocks that can be reused across stages, reducing the total circuitry area while maintaining high throughput through pipelined operation between stages.
Solution Approach 2:
The architecture dynamically switches between pipelined operation mode (for high throughput) and parallel operation mode (for reduced area utilization). This dynamic adaptation allows the system to optimize resource usage based on computational requirements, preventing the need for permanently allocated large circuitry areas.
2Speed
If parallel architectures are used to accelerate NTT computations, then computational speed is improved, but memory access overhead increases for providing polynomial coefficients
Solution Approach 1:
Polynomial coefficients are pre-loaded into on-chip memory buffers before the NTT computation begins. This preliminary action ensures that all necessary data is readily available in fast memory during the parallel computation phases, eliminating the need for repeated slow memory accesses and reducing overall memory access overhead.
Solution Approach 2:
On-chip memory buffers serve as an intermediary between the parallel processing units and the external memory system. These buffers hold coefficient data locally, allowing parallel processors to access data rapidly without generating excessive memory access traffic to external memory, thus reducing memory access overhead while maintaining high computational speed.
Data Source
AI summary
A cryptographic accelerator utilizes a combination of parallel and pipelined butterfly operator circuit to perform number theoretic transform (NTT) or inverse NTT (INTT.) The accelerator includes a first set of pipelined pairs of parallel butterfly operator circuits configured to operate on pairs of polynomial coefficients to provide output coefficients. A first buffer is coupled to store the output coefficients. A second set of pipelined pairs of parallel butterfly operator circuits are configured to operation on pairs of coefficients obtained from the first buffer to provide coefficients of the polynomial in a number theoretic transform (NTT) domain or out of the NTT domain.