Crystal Driver Duty Cycle Correction for Low-Jitter PLL Clocks
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Solution Overview
Problem
Existing duty cycle correction methods for low noise clock generation introduce more noise than the noise reduction gained by doubling the clock, leading to cycle-to-cycle jitter and preventing gain boost in charge pumps.
Innovation Solution
A method involving a detection circuit to measure the delay difference between edges of a doubled crystal oscillator clock and a phase-locked loop feedback clock, adjusting the duty cycle by programming the strength of a first stage amplifier and independently setting P-channel and N-channel driver strengths, and fine-tuning with a Schmitt trigger, without adding significant noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If duty cycle correction is performed using additional logic after the crystal amplifier, then the duty cycle of the input clock is corrected, but noise is added into the clock that negates the benefit of being able to double the input clock
Solution Approach 1:
The patent uses the Phase-Locked Loop (PLL) feedback clock as an intermediary reference to measure delay differences. Instead of directly measuring and correcting duty cycle using additional logic that adds noise, the system uses the PLL feedback clock as a clean reference signal to indirectly determine duty cycle errors through delay measurements, thereby avoiding direct intervention that would add noise to the clock path.
Solution Approach 2:
The patent implements a feedback mechanism where the PLL feedback clock is used to measure the delay difference between rising and falling edges of the doubled crystal oscillator clock. This feedback information about duty cycle errors is then used to control the delays of rising and falling edges independently, enabling continuous correction without adding significant noise to the clock signal.
2Productivity
If the input clock is not 50% duty cycle and is doubled, then the doubled clock can be generated, but considerable cycle-to-cycle jitter occurs which shows up as reference spur
Solution Approach 1:
The patent dynamically adjusts the delays of rising and falling edges based on measured duty cycle errors. The system continuously monitors the delay difference between clock edges using the PLL feedback reference and dynamically controls the edge delays to maintain 50% duty cycle, thereby eliminating cycle-to-cycle jitter while preserving clock doubling capability.
Solution Approach 2:
The patent changes the delay parameters of rising and falling edges independently based on measured duty cycle errors. By adjusting these delay parameters dynamically, the system corrects non-50% duty cycle conditions that would otherwise cause cycle-to-cycle jitter in the doubled clock, while maintaining the ability to generate doubled frequency output.
3Object-generated harmful factors
If gain boost is enabled in the charge pump, then noise performance is improved, but it cannot be used when cycle-to-cycle jitter is present
Solution Approach 1:
The patent performs preliminary duty cycle correction before the clock signal enters the charge pump stage. By measuring delay differences using the PLL feedback and correcting the rising and falling edge delays in advance, the system eliminates cycle-to-cycle jitter before it reaches the charge pump, thereby enabling gain boost mode operation and improving noise performance without compromising charge pump stability.
Data Source
AI summary
A method to generate a crystal oscillator clock having a duty cycle via a first stage of a clock circuit, double the crystal oscillator clock and inputting the doubled crystal oscillator clock into a phased-locked loop, feed back a phase-locked loop feedback clock, measure a difference in delay between a first edge of the doubled crystal oscillator clock relative to the phase-locked loop feedback clock and a second edge of the doubled crystal oscillator clock relative to the phase-locked loop feedback clock, and adjust the duty cycle of the crystal oscillator clock based on the difference in delay. A device having a detection circuit to measure a difference in delay between first and second edges of a doubled crystal oscillator clock output relative to a phase-locked loop feedback clock, and a controller to adjust the duty cycle of the clock output based on the difference in delay.