CSL Signal Generation Circuit for Stable DDR4 Pulse Width
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Solution Overview
Problem
Conventional CSL signal generation circuits in DDR4 chips face instability due to varying chip process corners, operating voltages, and temperatures, leading to fluctuating pulse widths that can cause data reading and writing failures.
Innovation Solution
A signal generation circuit comprising a clock delay circuit and a physical delay circuit, where the clock delay circuit delays an initial pulse signal by one or more clock cycles, and the physical delay circuit adjusts its delay duration to ensure the target signal's delay is within a preset range, thereby controlling the pulse width of the function pulse signal accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a physical delay circuit is used to generate CSL signal with pulse width independent of clock frequency, then the pulse width can be maintained across different clock frequencies, but the pulse width fluctuates in a large range due to unstable chip process corner, operating voltage and operating temperature
Solution Approach 1:
The delay circuit is divided into two independent parts: a clock delay circuit that delays the initial pulse signal by integer clock cycles, and a physical delay circuit that provides additional delay. This segmentation allows the clock delay circuit to handle the frequency-independent requirement while the physical delay circuit provides stable delay compensation, resolving the contradiction between adaptability and reliability.
Solution Approach 2:
The clock delay circuit acts as an intermediary between the initial pulse signal and the physical delay circuit. By introducing clock-cycle-based delay as an intermediate step, the system achieves both clock frequency independence and improved pulse width stability, as the clock delay provides a stable reference framework for the physical delay circuit.
2Manufacturing precision
If the preset delay duration of the physical delay circuit is set to achieve a target delay, then the target signal delay can be controlled, but the actual delay duration fluctuates due to process corner, voltage and temperature variations
Solution Approach 1:
The clock delay circuit provides a stable delay foundation before the signal enters the physical delay circuit. By pre-delaying the signal by integer clock cycles in a controlled manner, the system creates a stable baseline that cushions against subsequent variations in the physical delay circuit due to process, voltage, and temperature changes.
Solution Approach 2:
The system changes the delay parameter from being solely dependent on physical circuit characteristics to being a combination of clock-cycle-based delay and physical delay. This parameter transformation allows the total delay to be expressed as T_total = N×T_clock + T物理, where the first term provides stability and the second term provides precision adjustment.
Data Source
AI summary
Provided are a signal generation circuit and a memory. The signal generation circuit includes: a clock delay circuit for delaying an initial pulse signal to output an intermediate signal delayed by a first delay duration, the first delay duration being equal to one or more clock cycles; a physical delay circuit for delaying the intermediate signal to output a target signal, if an actual delay duration of the physical delay circuit is equal to a second delay duration, the target signal being delayed by a target duration, a difference between the actual and second delay durations fluctuating within a first preset range, and the shorter the second delay duration, the narrower the first preset range; and a generation circuit for outputting a function pulse signal having a pulse width equal to a time interval between rising edges of the initial pulse signal and the target signal.