Chip-Scale Package Ball Layout for Single-Layer PCB Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in providing signal routing channels for chip-scale packages (CSPs) on substrates, such as printed circuit boards (PCBs), is that as the number of IC contacts increases, it becomes difficult to design single-layer PCBs that can accommodate the pitch and clearance of CSP balls/bumps without violating design rules or causing short circuits, especially for central contact pads in multi-contact arrangements.
Innovation Solution
The solution involves creating a channel routing region within the CSP by using discontinuities in the arrangement of CSP contact balls or bumps, allowing for signal routing channels to be provided on a single-layer PCB without the need for costly high-density 'Via PCB' technology, by altering the CSP design to accommodate the substrate layout, which simplifies manufacturing and reduces costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer PCB is used with standard CSP ball arrangements, then manufacturing is simpler and costs are lower, but design rules are violated or short circuits occur due to insufficient clearance between signal routing channels and CSP balls
Solution Approach 1:
Instead of arranging CSP balls in a standard grid pattern and routing signals around them, the patent inverts the approach by first defining the signal routing channels and then positioning the CSP balls in the remaining spaces. This allows single-layer PCBs to route signals through discontinuities in ball rows without violating design rules or causing short circuits, while maintaining simple manufacturing processes
Solution Approach 2:
The patent segments the CSP ball arrangement into discrete rows with intentional discontinuities, allowing signal routing channels to pass through the gaps. This segmentation enables the PCB to maintain simple single-layer construction while ensuring reliable electrical connections by preventing short circuits between adjacent balls
2Reliability
If multilayer substrates are used to accommodate signal routing, then design rules are satisfied and short circuits are avoided, but manufacturing costs increase due to the complexity of high-density 'Via PCB' technology
Solution Approach 1:
The patent inverts the conventional approach by not using multilayer substrates with vias to resolve routing conflicts. Instead, it arranges balls in single-layer discontinuous patterns that naturally create routing channels, eliminating the need for costly high-density via technology while maintaining reliable electrical connections
3Area of stationary object
If the pitch and clearance of CSP balls are minimized to reduce footprint, then the CSP occupies less area on the PCB, but it becomes impossible to provide signal routing channels without violating design rules
Solution Approach 1:
The patent segments the ball arrangement into discontinuous rows with controlled gaps, allowing signal routing channels to exist within the CSP footprint without requiring additional PCB area. This segmentation enables compact design while maintaining manufacturability by providing clear paths for signal routing
Solution Approach 2:
The patent utilizes the two-dimensional arrangement of balls in discontinuous patterns to create routing channels, effectively using the planar dimension to solve the routing problem without requiring vertical dimension (multilayer) or excessive horizontal space
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient signal routing on a single-layer PCB, reducing the need for multilayer substrates and associated costs, while maintaining the compact footprint of CSPs, and allows for larger vias and greater tolerances in signal routing channel widths, facilitating simpler and less expensive manufacturing processes.
Implementation Method 1
applying heat to melt the solder to mechanically and electrically couple the IC contact pads to the corresponding substrate contact pads
Data Source
AI summary
The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.