Chip Scale Package Bump Gradient Design for Peeling and Bridging

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Solution Overview

Problem

The miniaturization of integrated circuit wafers and increasing integration of semiconductor devices lead to issues with bump peeling and bridging in Chip Scale Packages (CSPs), where bumps at the edge of the chip are prone to peeling due to stress and increased temperature variations, causing reliability and electrical property issues.

Innovation Solution

The semiconductor substrate is divided into regions based on distance from the central point, with contact bonding pads and bumps having smaller dimensions closer to the center and larger dimensions farther from the center, enhancing adhesion and reducing the likelihood of bridging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the volume of bumps is enlarged to maintain mechanical intensity, then the reliability of bumps is improved, but the bumps become larger and turn to lateral move causing bridging between bumps

Engineering Contradiction:
Improvebump reliabilityVSAvoidbridging between bumps
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by making different parts of the bump structure have different properties. Specifically, the bump structure includes a lower portion with larger diameter for mechanical strength and an upper portion with smaller diameter to prevent bridging. This gradient structure allows each region to serve its specific function: the broader base provides adhesion strength while the narrower top prevents lateral movement and bridging between adjacent bumps.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The bump structure is segmented into multiple portions with different diameters. The patent divides the bump into a lower portion and an upper portion, where the lower portion has a first diameter and the upper portion has a second diameter that is smaller than the first diameter. This segmentation allows the structure to simultaneously achieve mechanical strength through the larger lower portion and prevent bridging through the smaller upper portion.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If the distance between bumps is reduced to increase integration, then the chip size is reduced, but the bumps at the edge are liable to peel off due to greater stress

Engineering Contradiction:
Improvechip sizeVSAvoidbump adhesion
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent applies local quality by creating a gradient in bump dimensions across the chip surface. Bumps at different locations have different diameters, with edge bumps having larger lower portions to compensate for the greater thermal stress they experience. This localized adaptation allows the chip to maintain small overall size while ensuring reliable bump adhesion at stress-prone edge locations.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the physical parameters of bumps based on their location on the chip. The diameter of bumps varies according to their position, with the lower portion diameter being larger at edge locations compared to central locations. This parameter change allows the structure to adapt to varying stress conditions across the chip surface, maintaining reliability while enabling miniaturization.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the mechanical strength and reliability of bumps, preventing peeling and bridging, thus enhancing the performance and reliability of CSPs by optimizing bump dimensions and distribution.

Implementation Method 1

Bumps are the metal solder balls formed after reflowing under certain temperature

Methodology Applied
Scientific EffectReflowing: Melting

Data Source

PatentUS9059004B2Method for chip scale package and package structure thereof
Publication Date: 2015.06.16 SEMICON MFG INT (BEIJING) CORP
  • US9059004B2 patent drawing
  • US9059004B2 patent drawing
  • US9059004B2 patent drawing

AI summary

This invention provides a method for chip scale package and a chip scale package structure. The chip scale package structure includes: a semiconductor substrate, on which sets a plurality of contact bonding pads being connected with semiconductor devices; and a plurality of bumps respectively attached to all of the contact bonding pads. The semiconductor substrate is divided into several regions according to different distances from a central point. The contact bonding pads and the bumps in the region which is closest to the central point are the smallest, while the contact bonding pads and the bumps in the region which is farthest to the central point are the largest. The invention effectively improves the situation that the bumps at the edge tend to flake off easily; in addition, it avoids short-circuit caused by bridging between the bumps.