CTE-Matched Constraint Layer for LCP-HTCC Waveguide Interface

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional interface techniques between liquid crystal polymer (LCP) circuit boards and high temperature co-fired ceramic (HTCC) carriers face challenges due to significant differences in electrical, mechanical, and thermal properties, leading to high complexity, performance shortcomings, and increased manufacturing costs, especially at high frequencies like 45 GHz.

Innovation Solution

A low-cost, compact waveguide constraint interface is developed using a constraint layer with waveguide cavities that provides a coefficient of thermal expansion (CTE) match between LCP and HTCC substrates, allowing for efficient coupling and alignment, reducing manufacturing risks and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional interface techniques are used between LCP circuit boards and HTCC carriers, then electrical, mechanical and thermal properties can be connected, but the interface complexity increases and performance shortcomings occur

Engineering Contradiction:

Improveinterface performanceVSAvoidinterface complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A constraint layer is introduced as an intermediary component between the LCP circuit board and HTCC carrier. This constraint layer serves as a mediator that provides mechanical constraint and thermal expansion compensation, enabling reliable electrical, mechanical and thermal connection while avoiding the complexity of direct interfacing between the dissimilar substrates.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The constraint layer is constructed from composite materials specifically selected to match the coefficient of thermal expansion (CTE) between the LCP circuit board and HTCC carrier. This composite material approach allows the interface to handle thermal expansion differences without requiring complex compensation mechanisms, thereby reducing interface complexity while maintaining reliability.

Inventive Principle:

Principle #40Composite materials

2Reliability

If conventional interface techniques are used between LCP circuit boards and HTCC carriers, then connection can be established, but manufacturing costs increase due to extreme preciseness requirements

Engineering Contradiction:

Improveconnection reliabilityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The constraint layer is designed with specific geometric parameters and material properties that enable tolerance compensation. By carefully selecting the thickness, shape and CTE of the constraint layer, the interface can accommodate manufacturing variations in the LCP board and HTCC carrier without requiring extreme precision, thereby reducing manufacturing costs while maintaining connection reliability.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If conventional interface techniques are used between LCP circuit boards and HTCC carriers, then electrical connection can be made, but thermal sensitivity and alignment issues increase

Engineering Contradiction:

Improveelectrical connectionVSAvoidthermal sensitivity

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The constraint layer is specifically designed with a coefficient of thermal expansion that matches the average of the LCP circuit board and HTCC carrier. This thermal expansion matching allows the constraint layer to compensate for differential thermal expansion between the two substrates, reducing thermal sensitivity and alignment issues while maintaining reliable electrical connection across temperature variations.

Inventive Principle:

Principle #37Thermal expansion

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables high-performance, low-complexity, and cost-effective waveguide constraint interfaces that mitigate alignment and thermal sensitivity issues, supporting multiple board sizes and frequencies without requiring additional components, thus reducing manufacturing tolerances and costs.

Implementation Method 1

The constraint layer is configured to provide a coefficient of thermal expansion (CTE) match between the first and second substrates

Methodology Applied

Scientific EffectCoefficient of thermal expansion (CTE) match: Thermal Expansion

Data Source

PatentUS11223099B1Interface assembly with a CTE matched constraint layer

Publication Date: 2022.01.11 LOCKHEED MARTIN CORP

AI summary

An interface assembly includes a constraint layer formed from a material that provides a coefficient of thermal expansion match between first and second circuit board substrates. The constraint layer includes a waveguide cavity that extends between first and second opposing outer surface the constraint layer. The first and second circuit board substrates are respectively coupled to the first and second outer surfaces of the constraint layer via single ground connections. Portions of the first and second circuit board substrates are aligned with the waveguide cavity and positive connections are made between components of the first and second circuit boards through the waveguide cavity.