CTLE Equalizer Reference Voltage Stabilization

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Solution Overview

Problem

DDR4 memory interfaces face significant channel loss and signal reflection issues at high data rates, leading to distorted data reception, which existing equalization methods struggle to effectively compensate for, especially during power-up transitions.

Innovation Solution

A continuous-time linear equalizer (CTLE) circuit is implemented to compensate for channel loss and reflection, using a switch-controlled reference voltage generation to minimize disturbance from parasitic capacitance and improve signal integrity, with core voltage domain devices operating faster than I/O devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If equalization is implemented at power up, then signal integrity is improved, but reference voltage stability deteriorates due to parasitic capacitance coupling

Engineering Contradiction:

Improvesignal integrityVSAvoidreference voltage stability

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The reference voltage is generated and stabilized before the equalization circuit is activated. The power-up sequence ensures that the reference voltage reaches its stable state prior to enabling the CTLE equalization function, preventing parasitic capacitance coupling from affecting voltage stability during signal processing

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The power-up sequence is divided into distinct phases: first generating and stabilizing the reference voltage, then activating the equalization circuit. This segmentation separates the voltage stabilization function from the signal equalization function, allowing each to operate independently without interference

Inventive Principle:

Principle #1Segmentation

2Productivity

If data rate is increased to 3.2 Gbps, then storage capacity is improved, but channel loss and signal reflection become significant

Engineering Contradiction:

Improvedata rateVSAvoidchannel loss and signal reflection

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The equalization circuit continuously monitors the signal quality and adjusts its compensation parameters in real-time to counteract channel loss and signal reflection effects at high data rates, maintaining signal integrity as data rate increases

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The equalization parameters are dynamically adjusted based on the operating data rate. At higher data rates like 3.2 Gbps, the circuit modifies its frequency response and gain characteristics to compensate for increased channel loss and reflection effects

Inventive Principle:

Principle #35Parameter changes

3Reliability

If continuous-time linear equalization is applied, then data eye height and width are improved, but circuit complexity increases

Engineering Contradiction:

Improvedata eye qualityVSAvoidequalization circuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces complex discrete equalization stages with a continuous-time linear equalization approach that uses analog circuitry to achieve data eye improvement. This substitution reduces the number of discrete components while maintaining or enhancing performance

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9589626B1Single-ended memory signal equalization at power up

Publication Date: 2017.03.07 INTEGRATED DEVICE TECH INC

AI summary

An apparatus having a first circuit and a second circuit. The first circuit may be configured to buffer an input signal received as a single-ended signal from a data bus connected between a memory channel and a memory controller. The second circuit may be configured to condition the input signal relative to a reference voltage to generate a differential signal. The reference voltage may be isolated from the second circuit in response to a transition from a power down condition to a power on condition.