Digital Storage TRIZ Cases

A semiconductor memory device uses a time measurement unit to generate delay control signals that adjust column selection activation.

Pseudo static random access memory chips share collision signals to synchronize latency times across multi-chip packages.

A NAND gate write driver circuit integrates precharge and data transmission functions into a single block to reduce semiconductor chip area.

Segmenting the sensing circuit into independent paths reduces sensitivity to noise and process variations during read operations.

A down-conversion circuit couples a memory cell to a sense component via selective switching.

Analog synapse circuits reduce power consumption by replacing digital arithmetic with current summation and potential conversion.

A semiconductor write structure combines spin-orbit torque patterns with a conductive layer to lower electrical resistance.

Segmenting bit line equalization into precharge and write phases prevents write disturbances, reducing write time without increasing hardware area.

Selective refresh based on data validity tables reduces power consumption and extends access time.

Vertical stacking of storage and access transistors reduces SRAM cell area while maintaining data reliability and lowering power consumption.

An MRAM cell uses an electrostatic gate to modulate a semiconductor layer's resistance for spin-orbit torque operations.

Segmenting memory arrays with local read circuitry minimizes capacitive discharge that corrupts logic states and reduces readable operations.

A semiconductor memory device generates discrete set and reset master signals for independent test mode control.

Arbitration switch blocks enable simultaneous data access across serial ports, reducing pin count and power consumption in high-speed memory systems.

A semiconductor memory device aligns data using dynamic alignment signals generated from detected input speeds.

Segmenting recovery into rapid copy reads and parity calculations reduces reconstruction time while maintaining data reliability.

A memory cell selector element amplifies stored data using a negative-resistance property to counteract parasitic resistance in bit lines and word lines.

Straight-like layout with twin MOSFETs eliminates L-shape induced leakage while maintaining beta ratio in dual-port SRAM cells.

Josephson supercurrent diode detects domain walls via proximity magnetization, resolving speed and energy trade-offs.

A cantilever magnetoelectric thin film sensor uses a freestanding multilayer structure to generate piezo-induced voltage from magnetic fields.

A semiconductor device divides memory arrays into blocks with varying match line lengths to enable high-speed search operations.

A memory emulator uses single-port cells and mapping tables to emulate concurrent two-port read and write access.

A digital input buffer uses pulsed positive feedback to accelerate signal transitions and settle output states rapidly.

A magnetic device uses a ferroelectric layer to magnetoelectrically couple with a magnetic layer, creating or annihilating skyrmions without high current densities.

Segmenting read data into distinct bit widths via separate amplification and selection latch modules reduces redundant replacement circuits.

Multiple pre-charge voltages initialize bit lines, resolving instability from low power supply margins.

A power-on reset state machine coordinates address and data signals to pre-bias memory cells during integrated circuit initialization.

A memory controller trains dual channel DDR busses across multiple active and idle transaction modes to consolidate timing parameters.

A semiconductor device uses a shared memory interface with dual peripheral circuits to switch between LPDDR4 and LPDDR4X protocols based on voltage detection.

Auto-recovery memory synchronization uses integrated majority voting circuits to maintain data integrity during radiation-induced upsets.

A pre-charge transistor connects a global data line driver to a supply voltage.

A semiconductor memory device generates output enable signals by comparing DLL clock and external clock count values.

Pulse voltage generators suppress gate-induced drain leakage by applying dynamic frequencies that prevent large potential differences across the transistor.

An operation control circuit generates detection and internal masking signals to select converted or drive data for storage.

A continuous-time linear equalizer circuit conditions single-ended memory signals using a switch-controlled reference voltage generation mechanism.

A memory module control circuit switches volatile memory reference voltage from an external source to an internal generator.

Dual sensing current latched sense amplifier merges sensing and amplification functions into existing transistors to enhance voltage differential sensitivity.

A semiconductor memory device uses a sense amplification enable signal control portion to sequentially delay and selectively output multiple delayed signals for clocked regenerative amplifiers.

A bistable circuit paired with a ferromagnetic tunnel junction device stores data via current-induced magnetization reversal for high-speed access.

Segmenting the lookup table by data retention time reduces its size by up to 50% while ensuring frequent refresh of weak cells.

A ternary content addressable memory cell uses static logic gates to compare search data with stored content.

Integrating dummy magnetic tunneling junction structures within the logic region using metal interconnections to create short or open circuits.

Collective memory block disposition and centralized power routing reduce resistance and voltage drops while minimizing chip area.

A synchronous memory device uses a delayed flag signal to generate an enable pulse for internal address transfer.

A memory circuit generates a write acceptance signal to count strobe edges and adjust phase offset.

Threshold voltage modification expands voltage windows of borderline dice, reducing manufacturing waste and improving high-temperature data retention.

Air gaps between adjacent word lines lower permittivity to cut latency and power consumption.

Calculates delay parameters from setup time and target sampling delays to resolve misalignment errors in DRAM clock signal division.