MRAM Cell Electrostatic Gate Modulates Semiconductor Resistance
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Solution Overview
Problem
Existing magnetic random access memory (MRAM) cells face challenges in achieving high reading accuracy and reducing energy loss during memory cell reading due to high electrical resistance in the circuit, which affects the efficiency of spin-charge conversion and reading time.
Innovation Solution
Incorporating a semiconductor layer separated by an insulating layer from an electrostatic gate below the magnetic tunnel junction (MTJ), allowing the electrostatic gate to modulate the semiconductor resistance by applying a voltage, thereby increasing the MTJ resistance during reading and decreasing it during writing to enhance accuracy and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the MTJ resistance is increased to improve reading accuracy, then the reading accuracy improves, but the energy loss increases due to P=RI^2
Solution Approach 1:
The patent applies dynamics by making the semiconductor layer resistance可调 (adjustable) through voltage control via the electrostatic gate. The resistance can be dynamically increased during reading operations to improve accuracy, and decreased during writing operations to reduce energy loss, allowing the system to optimize performance based on operational mode
Solution Approach 2:
The patent changes the resistance parameter of the semiconductor layer by applying different voltages to the electrostatic gate. During reading, the gate voltage is adjusted to increase resistance for better accuracy. During writing, the resistance is reduced to minimize energy loss according to P=RI^2, directly addressing the contradiction between accuracy and energy consumption
2Productivity
If the SOT current layer length is increased to improve spin-charge conversion efficiency, then the conversion efficiency improves, but the writing current dispersion increases
Solution Approach 1:
The patent applies local quality by creating a high-resistance region specifically at the location of the SOT current layer through the semiconductor layer and electrostatic gate structure. This localized resistance enhancement concentrates the writing current precisely where needed in the SOT layer, preventing current dispersion even when the layer is long, thereby maintaining both conversion efficiency and current concentration
Solution Approach 2:
The semiconductor layer acts as an intermediary between the electrostatic gate and the SOT current layer. By modulating the semiconductor layer resistance through the gate, it mediates the current distribution to ensure concentrated writing current in the SOT layer, enabling efficient spin-charge conversion without current dispersion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves reading accuracy and reduces energy loss by concentrating the writing current and optimizing the resistance of the SOT current layer, especially beneficial for MRAM cells with long SOT current layers, leading to more efficient spin-charge conversion and reduced energy consumption.
Implementation Method 1
Applying a voltage to the electrostatic gate has the consequence to modify i.e. increase or decrease the resistance of the semiconductor layer by electrostatic coupling
Implementation Method 2
When the charge current 301 is flowing through the SOT current layer, a spin current is generated by spin orbit interaction for example by spin Hall effect and/or Rashba-Edelstein effect
Implementation Method 3
When the charge current 301 is flowing through the SOT current layer, a spin current is generated by spin orbit interaction for example by spin Hall effect and/or Rashba-Edelstein effect
Implementation Method 4
magnetic random access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ) element
Data Source
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AI summary
The present disclosure is about a magnetic random access memory (MRAM) cell (100), comprising a first magnetic tunnel junction (MTJ) element (10) comprising a tunnel barrier layer (22) between a reference layer (21) having a reference magnetization and a free layer (23) having a free magnetization that can be freely oriented, the reference and free layers (21, 23) having a perpendicular magnetic anisotropy (PMA); a SOT current layer (30) configured to pass a write current (301) adapted for switching the free magnetization by a spin current by SOT interaction. The MRAM cell (100) further comprises an electrostatic gate (50) configured to electrostatically interact with a semiconductor layer (40) disposed in direct contact to the SOT current layer 30 such that the semiconductor layer resistance can be modulated for read and/or write process.