Semiconductor Memory Output Enable Signal Generation
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Solution Overview
Problem
Conventional output enable signal generators in semiconductor memory devices face challenges with increased CAS latency, requiring expanded counter capabilities, leading to higher current consumption and unwanted delay times, and necessitate frequent reset operations due to changing initial count values.
Innovation Solution
A semiconductor memory device with a first output enable signal generating unit that compares DLL clock and external clock count values to produce a first output enable signal, and a final output enable signal generating unit that shifts this signal based on CAS latency, allowing for optimal current consumption and minimal delay without increasing initial count values or bit numbers, and eliminates unnecessary reset operations by reflecting CAS latency information on external clock counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the counter capability is expanded to handle increased CAS latency, then the device can accommodate higher latency values, but current consumption increases and delay times are extended
Solution Approach 1:
The patent divides the counter into multiple sub-counters (first counter, second counter, third counter) that operate in different clock domains. Each sub-counter handles a portion of the counting function, allowing the system to accommodate higher CAS latency without requiring a single large-capacity counter that would consume more current. The segmentation enables efficient resource utilization across clock domains.
Solution Approach 2:
The patent introduces a time dimension by using multiple clock domains (DLL clock domain and external clock domain) to perform counting operations. Instead of increasing the capacity of a single counter in one time domain, the solution distributes counting across multiple time domains, thereby accommodating higher CAS latency without proportionally increasing current consumption in any single domain.
2Adaptability or versatility
If the counter capability is expanded to handle increased CAS latency, then the device can accommodate higher latency values, but unwanted delay times are extended
Solution Approach 1:
The patent segments the delay accommodation function across multiple counters operating in different clock domains. The first counter operates in the DLL clock domain while the second and third counters operate in the external clock domain. This segmentation allows the system to handle variable CAS latency values without creating a single long delay path, thereby reducing unwanted delay times.
Solution Approach 2:
The patent implements dynamic counting where the counting process adapts to different CAS latency requirements by using different initial count values and operating in different clock domains. The system dynamically selects which counter to use and what initial value to load, allowing flexible latency accommodation without fixed, extended delay paths.
3Adaptability or versatility
If the initial count value is changed according to CAS latency, then the device can adapt to different latency requirements, but frequent reset operations are required
Solution Approach 1:
The patent segments the adaptation function across multiple counters, where each counter can be independently configured with different initial values. This allows the system to adapt to different CAS latency requirements by selecting appropriate counters and initial values without resetting the entire counting system, thereby reducing reset operation frequency.
Solution Approach 2:
The patent creates a universal counting system where multiple counters can serve different CAS latency requirements. The counters can be configured with different initial values and operate in different clock domains, allowing a single counter structure to handle multiple latency scenarios without requiring frequent resets and reconfigurations.
4Adaptability or versatility
If the bit number of counters is increased to handle higher CAS latency, then the device can accommodate higher latency values, but device complexity increases
Solution Approach 1:
The patent segments the high-latency counting function into multiple smaller counters operating in different clock domains. Instead of using a single high-bit counter that would increase device complexity, the solution uses multiple lower-bit counters (first counter, second counter, third counter) that work together to achieve the same functionality with reduced individual complexity.
Solution Approach 2:
The patent resolves the complexity issue by adding a clock domain dimension. Instead of increasing the bit width of counters in a single clock domain (which increases complexity), the solution distributes counting across multiple clock domains (DLL clock domain and external clock domain), thereby achieving higher CAS latency accommodation without proportionally increasing counter structure complexity.
Data Source
AI summary
A semiconductor memory device is capable of generating a desired output enable signal without increasing an initial count value and bit number and generating a desired final output enable signal, without unnecessary reset operations, by reflecting column address strobe (CAS) latency information on an external clock count value. The semiconductor memory device includes a first output enable signal generating unit and a final output enable signal generating unit. The first output enable signal generating unit is configured to compare a first count value, which is obtained by counting a delay locked loop (DLL) clock, to a second clock count value, which is obtained by counting an external clock until a read command is input, and to output a first output enable signal. The final output enable signal generating unit is configured to output a final output enable signal generated by shifting the first output enable signal, according to CAS latency.