Three-Layered SRAM Cell Design Reducing Footprint
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Solution Overview
Problem
SRAM devices have a large footprint due to the number of transistors required for each cell, leading to lower storage density and higher costs compared to DRAM devices, while also consuming high power during read/write operations.
Innovation Solution
The SRAM cell is designed with a three-layered stack of transistors using different semiconductor materials, reducing the footprint by distributing six transistors across three layers, with two storage transistors in each of two layers and two access transistors in the third layer, allowing for a smaller device size without impacting classical logic circuitry design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If six transistors are used in each SRAM cell (four storage transistors and two access transistors), then the SRAM cell can store and access data reliably, but the footprint of the SRAM cell becomes large
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. Six transistors are distributed across three vertical layers, with each layer containing two transistors. This vertical stacking reduces the horizontal footprint while maintaining all necessary transistor connections for reliable SRAM operation.
Solution Approach 2:
The SRAM cell is segmented into three distinct layer structures, with transistors distributed across these layers. The storage transistors and access transistors are separated into different layers, allowing independent optimization of each layer's function while reducing overall cell area.
2Area of stationary object
If the SRAM cell footprint is reduced by using fewer transistors or smaller transistor size, then the storage density increases, but the power consumption during read/write operations increases
Solution Approach 1:
Different semiconductor materials are used in different layers to optimize local properties. The first layer uses a first semiconductor material, the second layer uses a second semiconductor material, and the third layer uses a third semiconductor material. This allows each layer to be optimized for its specific function (storage vs. access) while maintaining low power consumption and high density.
3Area of stationary object
If the SRAM cell footprint is reduced, then the storage density increases, but the wiring complexity and RC delay increase
Solution Approach 1:
By stacking transistors vertically across three layers, the patent reduces horizontal wiring requirements. The vertical arrangement allows shared bit lines and word lines to serve multiple transistors, simplifying the interconnect structure and reducing RC delay despite the reduced footprint.
Data Source
AI summary
The present disclosure relates generally to static random-access memory (SRAM) devices. Specifically, the disclosure proposes a SRAM device with a three-layered SRAM cell design. The SRAM cell comprises a storage comprising four storage transistors, and comprises two access transistors to control access to the storage cell. The SRAM cell further comprises a stack of three layer structures. Two of the storage transistors are formed in a first layer structure of the stack, and two other of the storage transistors are formed in a second layer structure of the stack adjacent to the first layer structure. The two access transistors are formed in a third layer structure of the stack adjacent to the second layer structure. Each layer structure comprises a semiconductor material, the transistors in the layer structure are based on that semiconductor material, and at least two of the three layer structures comprise a different type of semiconductor material.