DRAM Refresh Control via Data Validity Tables
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Solution Overview
Problem
Dynamic random access memory (DRAM) requires frequent refresh operations to maintain data validity, leading to increased power consumption and reduced computing efficiency due to the need for the system to wait for refresh completion, especially as memory capacity grows and the memory cannot determine data validity independently.
Innovation Solution
A memory device and method that utilize a memory controller and storage circuits to maintain data tables and refresh values, allowing the system to determine data validity and send specific refresh commands to memory blocks, thereby avoiding unnecessary refresh operations and optimizing access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed periodically to maintain data validity in DRAM, then data reliability is improved, but power consumption increases and computing efficiency decreases
Solution Approach 1:
The patent applies partial action by performing refresh operations only on memory blocks that contain valid data. The memory controller checks the data table to determine which memory blocks have valid data, and then selectively refreshes only those blocks. This avoids the excessive action of refreshing all memory blocks periodically, thereby reducing power consumption while maintaining data reliability for valid data.
2Reliability
If refresh operations are performed periodically to maintain data validity in DRAM, then data reliability is improved, but computing efficiency decreases due to system idle time
Solution Approach 1:
The system performs refresh operations only on memory blocks containing valid data, as determined by checking the data table. This partial action reduces the time the system spends on refresh operations, allowing the system to remain productive longer and improving overall computing efficiency while maintaining data validity.
Solution Approach 2:
The patent implements a feedback mechanism where the memory controller continuously monitors the data table to determine which memory blocks contain valid data. Based on this feedback information, the controller dynamically adjusts refresh operations, enabling intelligent decision-making about which blocks need refreshing, thereby optimizing the balance between data reliability and computing efficiency.
3Reliability
If all memory blocks are refreshed periodically, then data validity is maintained, but access time increases and data bandwidth decreases
Solution Approach 1:
The patent applies partial action by refreshing only the subset of memory blocks that contain valid data, as identified through the data table. This selective approach reduces the total refresh time required, thereby decreasing access time loss and increasing available data bandwidth for actual computational operations.
4Productivity
If the memory controller monitors data validity in all memory blocks, then refresh operations can be optimized, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory system into two functional parts: the memory array and the memory controller with its data table. The data table is segmented into entries corresponding to individual memory blocks, allowing the controller to monitor and manage data validity on a block-by-block basis. This segmentation enables efficient tracking of valid data locations without requiring complex monitoring of the entire memory space, thus optimizing refresh operations while controlling device complexity.
Data Source
AI summary
A memory device includes a memory with a plurality of memory blocks and a first storage circuit to store a first data table and a first refresh value, and a memory controller with a second storage circuit to store a second data table and a second refresh value. When the memory controller meets a refresh request, the memory controller reads the second refresh value and compares the corresponding access address to the corresponding bit in the second data table to determine whether valid data are stored in a specific memory block of the memory. The memory controller sends a valid-data refresh command to the memory when valid data are stored in the specific memory block, but sends an invalid-data refresh command to the memory when invalid data are stored in the specific memory block.