Pulsed Positive Feedback Input Buffer for Digital Signal Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Input buffers in digital circuits, such as those used in memory devices, introduce significant propagation delays due to internal capacitances, which limit the operating speed of integrated circuits as they increase in speed.
Innovation Solution
A digital signal input buffer design that incorporates positive feedback responsive to each input signal transition, with the feedback terminating before the next transition, and uses a delay circuit to manage the feedback, allowing the output signal to quickly settle and prevent latching issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional input buffer circuits are used, then signal conditioning and logic level definition are achieved, but propagation delay increases significantly due to internal capacitances
Solution Approach 1:
The patent applies periodic pulsed feedback action to the input buffer circuit. A feedback signal is periodically applied to the input of the buffer circuit in synchronization with the input signal transitions. This pulsed feedback accelerates the charging and discharging of internal capacitances during signal transitions, thereby reducing propagation delay while maintaining proper signal conditioning and logic level definition throughout the circuit operation.
2Speed
If positive feedback is applied to reduce delay, then signal transition speed increases, but latching or bi-stable behavior may occur
Solution Approach 1:
The feedback is applied periodically only during specific phases of the input signal cycle, specifically during transitions, rather than continuously. This timed application provides the beneficial speed-up effect during critical moments while avoiding continuous reinforcement that would cause latching or bi-stable behavior.
Solution Approach 2:
The patent uses controlled positive feedback by applying a feedback signal to the input of the buffer circuit that reinforces the input signal during transitions. This feedback mechanism accelerates the response time of the buffer circuit by reducing the effective time constant during transitions, while the controlled nature of the feedback prevents unstable latching behavior.
3Loss of time
If buffer circuit capacitances are reduced, then propagation delay decreases, but signal gain and driving capability are compromised
Solution Approach 1:
Instead of permanently reducing capacitance values, the patent applies periodic feedback pulses that actively manage the charging and discharging of the buffer circuit's internal capacitances. This approach reduces the effective time constant during transitions without permanently altering the capacitance values, thereby maintaining both fast response and adequate signal gain capability.
Solution Approach 2:
The feedback signal acts as an intermediary that mediates between the input signal and the buffer circuit's internal capacitances. By providing additional charge/discharge pathways through the feedback mechanism, the system achieves faster transitions without needing to reduce the physical capacitance values, thus preserving signal gain and driving capability.
Data Source
AI summary
An input buffer generates an output signal corresponding to a digital input signal. The input buffer is coupled to a feedback circuit. The feedback circuit initially couples a positive feedback signal to the buffer circuit responsive to each transition of the input signal. The positive feedback signal increases the gain of the input buffer thereby causing the input buffer to transition the output signal more quickly in response to the transition of the input signal. The feedback circuit thereafter terminates the positive feedback signal before a subsequent transition of the input signal. The positive feedback signal is generated by detecting a transition of the output signal responsive to the transition of the input signal that initiated the positive feedback signal.