DRAM Clock Signal Division Delay Parameter Determination
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Solution Overview
Problem
In DRAM design, the division of the clock signal into four stage signals often results in delays, leading to erroneous DQ data collection due to misalignment of write data signals with clock sub-signals.
Innovation Solution
A method and apparatus for determining a delay parameter by calculating the setup time of a clock signal relative to a DQ data signal, dividing the clock signal into clock sub-signals, and determining a target sampling delay to ensure correct data sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock signal is divided into four stage signals for data acquisition, then the data sampling capability is improved, but signal delay and misalignment occur leading to erroneous data collection
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-adjusting the delay parameter based on the setup time and target sampling delay before actual data acquisition occurs. The delay parameter is determined in advance through the formula: delay parameter = target sampling delay - setup time, ensuring that the DQ data signal is properly aligned with the clock sub-signals before sampling begins, thereby preventing misalignment and erroneous data collection
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the delay parameter of the DQ data signal relative to the clock signal. By changing the timing parameter of the data signal based on the calculated delay, the system compensates for the division of the clock signal into four stages, ensuring proper synchronization and eliminating data sampling errors
2Ease of manufacture
If manual measurement methods are used to determine delay parameters, then the measurement process is simple, but measurement accuracy and reliability are compromised
Solution Approach 1:
The patent applies self-service by enabling the system to automatically determine its own delay parameter without requiring external manual measurement. The system uses its internal clock signal division and setup time information to self-calculate the delay parameter through the formula: delay parameter = target sampling delay - setup time, thereby eliminating the need for manual intervention while maintaining high measurement precision
Solution Approach 2:
The patent replaces manual measurement mechanisms with an automated electronic calculation system. Instead of relying on physical or manual timing measurements, the system uses electronic signal processing and mathematical calculation to determine the delay parameter, thereby improving precision while maintaining ease of implementation through automated computation
Data Source
AI summary
A method and an apparatus for determining a delay parameter, a computer readable storage medium, and an electronic device are provided. The method for determining the delay parameter includes: determining (S210) a setup time of a clock signal in a memory relative to a DQ data signal; dividing (S220) the clock signal into a plurality of clock sub-signals, and determining (S220) a target sampling delay of the plurality of clock sub-signals relative to the DQ data signal; and determining (S230), according to the target sampling delay and the setup time, a delay parameter of the DQ data signal relative to the clock signal.