Memory Emulator Using Single-Port Cells and Mapping Tables

The patent segments the memory system into multiple single-port memory banks (first plurality and second plurality of memory cells) that can be independently accessed. This segmentation allows the system to achieve multi-port functionality through software-controlled access patterns rather than hardware-level multi-port cells, thereby reducing the transistor count and chip area required for each individual memory cell while maintaining the ability to perform concurrent read and write operations across different ports.

By dividing the memory into separate single-port memory banks, the patent reduces the number of transistors that need to be simultaneously active for multi-port operations. Each memory bank can be accessed independently, allowing the system to achieve multi-port functionality with lower power consumption compared to a monolithic implementation where additional transistors for each port would require simultaneous operation.

The patent segments the memory access paths into separate single-port memory banks, which simplifies the internal structure of each memory cell and reduces the complexity of concurrent access control. This segmentation allows for more straightforward read and write operations with fixed latency, improving overall performance compared to a monolithic multi-port memory where increased transistor count and access control complexity would degrade productivity.

The patent employs a controller that pre-manages memory bank selection and mapping before actual data access occurs. By establishing the mapping between logical ports and physical memory banks in advance, and by using dedicated checksum modules for error detection, the system minimizes access latency when actual read or write operations occur, despite using simpler single-port memory cells.