Dual Channel DDR Memory Training for Signal Integrity
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Solution Overview
Problem
Dual channel DDR memory devices face challenges in maintaining high signal integrity during training due to cross-talk and noise effects, particularly when one command/address bus is active and the other is idle, or when one data bus is performing a write transaction while the other is performing a read or is idle, which existing training methods fail to adequately address.
Innovation Solution
A memory controller is configured to initiate various training modes, including C/A active-active, C/A active-idle, data write-write, data write-read, data write-idle, data read-read, data read-write, and data read-idle training, to consolidate training parameters into a single 'best fit' or 'worst case' parameter for use in normal operations, ensuring comprehensive training across different transaction modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing training methods are used for dual channel DDR memory devices, then training process is simpler, but signal integrity deteriorates due to unaddressed cross-talk and noise effects
Solution Approach 1:
The training process is segmented into multiple distinct training modes (C/A active-active, C/A active-idle, data write-write, data write-read, data write-idle, data read-read, data read-write, data read-idle) to address different transaction scenarios separately. Each mode targets specific cross-talk and noise conditions, allowing the system to manage complexity through structured decomposition rather than attempting to handle all conditions simultaneously in a single training process.
Solution Approach 2:
The patent implements preliminary training actions before normal operations begin. By conducting comprehensive training in all eight modes beforehand, the system pre-adjusts timing parameters and signal characteristics to compensate for cross-talk and noise effects that will occur during actual data transactions, ensuring signal integrity is established before production workloads begin.
2Reliability
If comprehensive training in all transaction modes is implemented, then signal integrity improves, but training time increases
Solution Approach 1:
The training process utilizes parameter changes by adjusting timing parameters, voltage levels, and signal characteristics for each training mode. By systematically varying these parameters across the eight different transaction scenarios, the system optimizes signal integrity for each specific condition. The consolidated training parameters generated through these parameter changes enable the system to achieve comprehensive coverage without requiring proportional increases in training time for each individual mode.
Solution Approach 2:
The training process incorporates feedback mechanisms where the memory controller monitors signal quality and transaction completion during each training mode. Based on this feedback, the system identifies the 'best fit' or 'worst case' parameters that provide sufficient signal integrity margin. This feedback-driven optimization allows the system to stop training once adequate parameters are found in each mode, reducing overall training time while maintaining reliability.
Data Source
AI summary
A memory channel includes a dual channel double data rate (DDR) memory device having a first bank of memory accessed by a first data bus and a first command/address (C/A) bus, and a second bank of memory accessed by a second data bus and a second C/A bus, and a memory controller configured to train the first and second C/A busses with both the first and second C/A busses active, and to train one of the first and second C/A busses with the other of the first and second C/A busses idle.