Variable Pre-Charge Levels for Memory Cell Stability
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Solution Overview
Problem
Memories in System-on-a-Chip (SoC) designs face instability and performance issues due to lower power supply voltages, which can cause unintended data state changes in data storage cells, especially when combined with manufacturing variations in MOSFETs, leading to sub-optimal operation of sense amplifiers and data storage cells.
Innovation Solution
The implementation of a memory circuit with multiple pre-charge voltages and a control circuit to manage these voltages based on control signals, including a start-of-access signal and a signal dependent on the decoded address, to improve the stability of data storage cells by initializing bit lines to specific voltage levels before access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If power supply voltage is reduced to accommodate thinner insulating layers, then manufacturing precision is improved, but reliability deteriorates due to insufficient voltage margin for proper circuit operation
Solution Approach 1:
The patent applies parameter changes by introducing multiple pre-charge voltage levels (first pre-charge voltage and second pre-charge voltage) to compensate for the reduced voltage margin caused by lower power supply voltages. The control circuit selectively applies different pre-charge voltages to bit lines based on operation type, ensuring reliable circuit operation while maintaining the benefit of reduced insulating layer thickness for manufacturing precision.
2Device complexity
If single pre-charge voltage is used to simplify circuit design, then device complexity is reduced, but reliability deteriorates due to inability to handle different operation requirements
Solution Approach 1:
The patent applies dynamics by making the pre-charge voltage level dynamic and adaptive rather than fixed. The control circuit dynamically selects between first and second pre-charge voltages based on the operation type (read vs. write), allowing the system to adapt to different operational requirements and maintain data storage cell stability without excessive complexity.
Solution Approach 2:
The patent changes the voltage parameter of the pre-charge circuit based on operational context. By providing multiple pre-charge voltage levels and selectively applying them through a control circuit, the system achieves reliable data storage cell operation for different operation types while keeping the overall circuit design manageable.
3Use of energy by moving object
If lower power supply voltage is used to reduce power consumption, then energy usage is improved, but manufacturing precision deteriorates due to increased sensitivity to MOSFET variations
Solution Approach 1:
The patent compensates for MOSFET performance variations caused by lower power supply voltages by introducing multiple pre-charge voltage levels. The control circuit selects appropriate pre-charge voltages to ensure sufficient voltage margins during read and write operations, thereby maintaining manufacturing precision and MOSFET performance consistency while benefiting from reduced power consumption.
Data Source
AI summary
Embodiments of a memory device are disclosed that may allow for multiple pre-charge voltages. The memory device may include a plurality of data lines, and a plurality of pre-charge circuits. Each of the plurality of data lines may be coupled to a plurality of data storage cells. Each of the plurality of pre-charge circuits may be coupled to a respective data line, and be configured to charge the data line to a first voltage level responsive to a first control signal. Each of the plurality of pre-charge circuits may also be configured to charge the respective data line to a second voltage responsive to a second control signal.