Storage Chip Read Operation Redundant Circuit Reduction

The patent segments the read data into two parts: a first bit width (MSBs) that is latched by first latches in the sensitive amplification module, and a second bit width (LSBs) that is latched by second latches in the selection latch module. This segmentation allows the system to achieve high read speed through the first bit width while reducing the number of redundant replacement circuits needed for the second bit width, as the second latches can be shared across multiple first latches.

The patent introduces a hierarchical latch structure that operates in multiple dimensions: first latches handle the most significant bits for high-speed reading, while second latches handle the least significant bits with reduced redundancy requirements. This dimensional division allows the system to optimize for both speed and circuit complexity by assigning different bit widths to different latch stages.

The patent segments the latch functionality into two distinct modules: a sensitive amplification module with first latches for the first bit width, and a selection latch module with second latches for the second bit width. This segmentation allows the chip area to be optimized by concentrating the high-speed reading functionality in the first module while using more efficient shared second latches for the remaining bits, thereby reducing the overall area compared to a uniform high-bit-width design.

The second latches in the selection latch module serve multiple functions: they latch the second bit width data, provide redundancy for the least significant bits, and can be shared across multiple first latch outputs. This multi-functionality reduces the total number of latch circuits needed, thereby reducing the chip area while maintaining high read operation speed through the first bit width path.

The patent segments the redundancy requirement by assigning first latches to handle the most significant bits where redundancy is less critical for yield, and second latches to handle the least significant bits where redundancy provides the most benefit for yield. This segmentation allows the wiring complexity to be reduced because the second latches can be shared across multiple first latch outputs, creating a hierarchical wiring structure that is simpler than a fully parallel redundant structure.

The patent introduces a hierarchical dimension to the redundancy structure: first latches operate at the MSB level with direct wiring to sensitive amplifiers, while second latches operate at the LSB level with shared wiring from multiple first latches. This dimensional hierarchy reduces wiring difficulty by organizing redundancy circuits in a tree-like structure rather than a fully parallel structure, thereby maintaining chip yield improvement while reducing wiring complexity.