Pseudo SRAM Latency Synchronization via Collision Signal Sharing
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Solution Overview
Problem
In multi-chip package architectures, pseudo static random access memory chips face challenges in adjusting latency times due to varying refresh collision occurrences, leading to operational difficulties and reduced execution speed.
Innovation Solution
A memory system where pseudo static random access memory chips share collision signals to synchronize latency times, allowing for real-time adjustment between short and long latency modes based on refresh collision presence or absence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If each pseudo static random access memory chip independently determines refresh collision and adjusts latency time, then the memory chip can optimize its own operation speed, but the multi-chip package system experiences operational complexity and synchronization difficulties
Solution Approach 1:
The patent merges the latency control functions of multiple pseudo static random access memory chips into a unified system. By sharing collision signals between chips, they collectively determine a common latency time, transforming individual independent decisions into a coordinated group action that simplifies control while maintaining optimization capability.
Solution Approach 2:
The patent implements a feedback mechanism where each memory chip monitors its own refresh collision status and shares this information with other chips through collision signals. This feedback loop enables the system to dynamically adjust latency time based on real-time collision conditions across all chips, resolving the synchronization problem.
2Reliability
If a long latency time is adopted to avoid refresh collision impact, then refresh collision problems are resolved, but the execution speed of memory operations decreases
Solution Approach 1:
The patent applies dynamics by making the latency time adjustable rather than fixed. The system can switch between long latency mode (when refresh collisions occur) and short latency mode (when no collisions occur), allowing optimal performance under different operating conditions and resolving the trade-off between reliability and speed.
Solution Approach 2:
The patent changes the latency time parameter dynamically based on refresh collision detection. By monitoring collision conditions and adjusting the latency parameter accordingly, the system achieves both refresh collision avoidance and maintained execution speed, eliminating the need for a fixed conservative latency setting.
3Productivity
If different latency times are used for different memory chips in multi-chip package, then each chip can be optimized individually, but real-time adjustment becomes difficult and control complexity increases
Solution Approach 1:
The patent creates a universal latency control mechanism that serves all memory chips in the multi-chip package simultaneously. By sharing collision signals and using a common latency time for all chips, the system maintains individual chip optimization capability while enabling easy real-time adjustment through a unified control approach.
Data Source
AI summary
A memory system and an operating method thereof are provided. The memory system includes a plurality of pseudo static random access memory chips and a memory controller. The pseudo static random access memory chips are coupled to each other. When receiving an action command, each of the pseudo static random access memory chips determines whether a refresh collision occurs in itself, and generates a collision signal accordingly. The memory controller controls the pseudo static random access memory chips according to the collision signal. All of the pseudo static random access memory chips share their respective collision signals to perform a same latency synchronously.