Semiconductor Memory Device Individual Test Item Reset
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Solution Overview
Problem
Conventional semiconductor memory devices require resetting all test mode MRS items simultaneously, making it impossible to individually reset test items, leading to repetitive and time-consuming test mode entry and experimentation processes.
Innovation Solution
A semiconductor memory device with a control signal generator, set/reset signal generator, test logic portion, and test control signal generator that allows for individual test item resets by using a discrete set/reset master signal, enabling independent control of test mode MRS units and reducing the need for repetitive test mode entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a conventional test mode semiconductor memory device is used, then all test mode MRS items are reset simultaneously, but it is impossible to individually reset test items, leading to repetitive test mode entry
Solution Approach 1:
The patent segments the test mode MRS reset function by providing separate reset signals for different test items. Instead of a single simultaneous reset for all test mode MRS items, the invention introduces individual reset control for each test item (e.g., first test mode MRS and second test mode MRS), allowing selective resetting without affecting other test items. This segmentation enables efficient retesting of specific items without repetitive test mode entry.
2Adaptability or versatility
If all test mode MRS items are reset simultaneously, then the test mode can be controlled uniformly, but individual test item reset is not possible, requiring repetitive test mode entry
Solution Approach 1:
The test control signal structure is segmented into multiple independent reset signals. The patent introduces a first reset signal for the first test mode MRS and a second reset signal for the second test mode MRS, allowing independent control of each test item's reset operation. This segmentation increases adaptability by enabling selective resetting while managing complexity through a systematic signal distribution architecture.
Solution Approach 2:
The reset signal generator is designed with multi-functionality to produce different types of reset signals. The same generator circuit can output both simultaneous reset signals (for uniform control) and individual reset signals (for selective control), making the device adaptable to different testing scenarios without requiring separate control mechanisms for each case.
3Productivity
If simultaneous reset of all test mode MRS items is performed, then test mode control is simplified, but test efficiency decreases due to inability to individually reset items
Solution Approach 1:
By segmenting the reset control into individual signals for each test mode MRS item, the patent enables efficient retesting of specific items. The first reset signal and second reset signal can be activated independently, allowing testers to quickly retest failed items without resetting or re-entering the test mode for all items, thereby significantly improving test efficiency while maintaining ease of operation.
Data Source
AI summary
A semiconductor memory device includes a control signal generator for combining command signals applied from an external portion to generate a test signal; a set/reset signal generator for receiving a mode setting signal applied from an external portion in response to the test signal and generating a first set/reset signal when the mode setting signal is a signal that designates an individual set/reset; a test logic portion for storing and then outputting the mode setting signal in response to the test signal; a set/reset master signal generator for receiving the first set/reset signal to output a set/reset master signal for commonly controlling a test mode of internal blocks of the semiconductor memory device; and a test control signal generator for combining an output signal of the test logic portion to generate a plurality of control signals and generating the set/reset master signal as a plurality of test control signals in response to the plurality of control signals.