Synchronous Memory Enable Signal Timing Control
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Solution Overview
Problem
Synchronous semiconductor memory devices face issues with generating internal addresses reliably, especially at high system clock frequencies, leading to insufficient margins for column address decoding and potential data access errors.
Innovation Solution
Incorporating an internal operation detecting unit to generate a flag signal, delaying it for a programmed time, and using an enable signal generating unit to activate and deactivate based on transition timings, ensuring reliable internal address transfer to the core area regardless of system clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the system clock frequency is increased to improve data processing speed, then productivity is improved, but the margin for column address decoding becomes insufficient leading to data access errors
Solution Approach 1:
The patent applies preliminary action by generating the column address enable signal before the column address decoding process begins. The signal is generated based on the command signal and address signal inputs, preparing the decoding circuitry in advance. This ensures that the decoding process has sufficient time to complete even at high clock frequencies, preventing data access errors while maintaining high productivity.
2Duration of action of moving object
If the clock buffer delays the system clock to generate an internal clock signal, then the internal operation timing is adjusted, but the margin for address decoding becomes insufficient at high frequencies
Solution Approach 1:
The patent introduces an intermediary column address enable signal that mediates between the command signal and the column address decoding process. This enable signal acts as a control intermediary that activates the decoding circuitry at the appropriate time, ensuring sufficient decoding margin independent of the internal clock delay. The intermediary signal coordinates the timing between clock generation and address decoding to maintain reliability.
3Stability of the object's composition
If the column address enable signal width is determined by the internal clock signal width, then the signal timing is synchronized, but insufficient margin occurs at high system clock frequencies
Solution Approach 1:
The patent applies parameter changes by making the column address enable signal width independent of the internal clock signal width. Instead of being determined by the clock signal duration, the enable signal width is determined by the command signal and address signal inputs. This parameter change allows the decoding circuitry to have sufficient time to operate correctly even when the internal clock frequency is high, while maintaining stable signal timing synchronization through the intermediary enable signal.
Data Source
AI summary
A synchronous semiconductor memory device can perform an internal operation for an input address with reliability regardless of the frequency of a system clock. The semiconductor memory device includes an internal operation detecting unit for generating a flag signal in response to internal command signals; a delay unit for delaying the flag signal for a programmed time; and an enable signal generating unit for generating an enable signal activated in response to a transition timing of the flag signal and inactivated in response to a transition timing of the delayed flag signal, wherein an internal address derived from an external address is transferred to a core area while the enable signal is activated.