Memory Cell Power-Up Sequence Control via POR State Machine
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Solution Overview
Problem
Advanced memory cells in integrated circuits face challenges in achieving a guaranteed logic state during power-up sequences due to reduced I/O interfaces and the absence of local reset circuitry, leading to difficulties in biasing memory cells correctly.
Innovation Solution
A method and apparatus that involve activating a first power supply, deasserting data input signals, clamping a second power supply to zero volts, and asserting address signals to bias memory cells during the power-up sequence, utilizing a power-on reset state machine and address drivers to ensure memory cells are pre-biased to known logic states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If I/O interfaces are reduced to simplify memory cell design, then device complexity is reduced, but the ability to guarantee logic state during power-up deteriorates
Solution Approach 1:
The patent applies preliminary action by establishing the logic state of memory cells before the main power-up sequence begins. Specifically, the address lines are asserted to select the appropriate memory cell, and the data input is pre-configured to the desired logic level before the clock signal is activated. This ensures that when power is applied, the memory cell is already in the correct state, eliminating the need for complex post-power-up initialization circuitry.
Solution Approach 2:
The patent uses an intermediary approach by introducing a control circuit that mediates between the simplified memory cell interface and the requirement for reliable logic state establishment. This control circuit coordinates the timing of address line assertion, data input configuration, and clock activation to ensure proper initialization without requiring additional I/O interfaces on the memory cell itself.
2Device complexity
If local reset circuitry is removed to reduce hardware complexity, then device complexity is reduced, but the ability to bias memory cells to known states during power-up deteriorates
Solution Approach 1:
The patent applies the extraction principle by removing the local reset circuitry from the memory cell and relocating the reset functionality to an external control circuit. This separates the memory cell's core storage function from the initialization function, allowing the memory cell to remain simple while the external control circuit handles the complex timing and state establishment requirements during power-up.
Solution Approach 2:
The patent implements multi-functionality by designing the external control circuit to perform multiple functions: it manages address line assertion, configures data input values, controls clock activation, and establishes the initial logic state. This single control circuit replaces what would have been multiple separate local reset circuits, reducing overall hardware complexity while maintaining reliable initialization.
3Reliability
If additional logic pull-downs are added within repeater cells to ensure logic state, then reliability of logic state is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by establishing the logic state before the repeater cells need to maintain it. The external control circuit pre-configures the memory cell inputs and addresses the cell in advance, so that when the repeater cells become active during normal operation, the logic state is already established and does not require additional pull-down circuitry to maintain.
Data Source
AI summary
A method and apparatus is provided to enhance the power-up sequence for integrated circuits (ICs) that contain memory cells having single-ended data inputs with no local reset function. During a power-up sequence, the logic levels that are applied to the data, address, and power inputs of the memory cell are restricted to particular magnitudes by a power-on reset (POR) state machine. First, the data input of the memory cell is held to a logic low value while an address signal of the memory cell is allowed to be asserted to a logic high value in conjunction with activating a power supply that provides operational power to the IC. Next, the address input to the memory cell ramps up to full logic high value, while the regulated power supply to the memory cell array is held low. The regulated power supply then ramps up to an operational level to bias the memory cell into a known logic state.