Semiconductor Integrated Circuit Memory Block Power Routing
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Solution Overview
Problem
Conventional semiconductor integrated circuits experience reduced wire efficiency and increased chip area due to irregularly spaced power terminals and complex power wire routing, leading to increased resistance and voltage drops.
Innovation Solution
Collective disposition of memory macros as a memory block on the semiconductor chip with separate power wire routing for logic and memory circuits, optimizing wire placement and reducing resistance, and sharing power circuit macros to minimize area and enhance layout efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory macros are disposed separately with individual power terminals, then power supply to each memory macro is ensured, but wire efficiency declines and chip area increases
Solution Approach 1:
Multiple memory macros are collectively disposed as a single memory block on the semiconductor chip, and a single power terminal is provided for the entire memory block rather than individual power terminals for each memory macro. This merging approach simplifies the power wire routing structure, reduces wire resistance, and improves wire efficiency while maintaining reliable power supply to all memory macros through the shared power terminal and distributed power wire network.
2Reliability
If power terminals are placed at irregular intervals around memory macros, then each memory macro receives power, but power wire resistance increases and voltage drops occur
Solution Approach 1:
The patent transitions from a distributed arrangement of power terminals around individual memory macros to a centralized power terminal arrangement for the entire memory block. Power wires are routed in an organized manner from the single power terminal to各个memory macros within the block, optimizing the wire length and reducing resistance by eliminating the need for irregularly spaced power terminals and their associated complex wire routing.
3Power
If separate power circuit macros are provided for each memory macro, then power generation is ensured, but chip area increases
Solution Approach 1:
Instead of providing separate power circuit macros for each memory macro, the patent implements a single power terminal that serves the entire memory block collectively. This universal power supply approach reduces the chip area by eliminating redundant power circuit macros while maintaining the power generation and distribution capability needed to support all memory macros within the block through a shared power infrastructure.
Data Source
AI summary
A plurality of memory macros, to which first power is supplied, and a logic circuit block, to which second power is supplied, are provided. The memory macros are collectively disposed as a memory block on a semiconductor chip, and memory power wires for supplying the first power to the memory macros that form the memory block are provided over the memory block.