Semiconductor Memory Sense Amplifier Timing Control
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Solution Overview
Problem
Semiconductor memory devices face a tradeoff between manufacturing yield and operation speed due to the timing of the sense amplification enable signal, with clocked regenerative amplifiers requiring a balance to maintain sufficient amplification until stable input signals are guaranteed.
Innovation Solution
A semiconductor memory device with a sense amplification enable signal control portion that sequentially delays the initial sense amplification enable signal by predetermined time periods and selectively outputs delayed signals to manage both operation speed and manufacturing yield, utilizing multiple clocked regenerative amplifiers and a previous-step output driving circuit to ensure timely and accurate data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sense amplification enable signal transitions to high level early to improve operation speed, then the operation speed characteristic is improved, but the manufacturing yield decreases due to insufficient time margin for stable input signal
Solution Approach 1:
The patent divides a single sense amplification enable signal into multiple segmented enable signals (first sense amplification enable signal and second sense amplification enable signal) with different timing characteristics. The first signal has an earlier transition time for speed improvement, while the second signal has a later transition time for yield improvement, allowing the system to utilize both timing characteristics simultaneously through multiple clocked regenerative amplifiers.
2Reliability
If the sense amplification enable signal transitions to high level late to improve manufacturing yield, then the manufacturing yield is improved, but the operation speed characteristic is degraded
Solution Approach 1:
The patent segments the sense amplification function into multiple parallel amplifiers with different enable signal timing. The second sense amplification enable signal transitions later to ensure manufacturing yield, while the first signal transitions earlier to maintain operation speed, and both are processed in parallel to achieve both objectives.
3Device complexity
If a single clocked regenerative amplifier is used, then the device complexity is low, but it cannot simultaneously achieve both high operation speed and high manufacturing yield
Solution Approach 1:
The patent segments the amplification function into multiple clocked regenerative amplifiers (first and second amplifiers) that operate in parallel with different enable signal timing characteristics, allowing the system to achieve both high speed and high yield simultaneously while maintaining relatively simple individual amplifier designs.
Solution Approach 2:
Multiple identical clocked regenerative amplifier circuits are used to perform different functions - one optimized for speed and another for yield - demonstrating how universal amplifier designs can be deployed in multiple instances to achieve diverse performance characteristics.
Data Source
AI summary
A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level is disclosed. The semiconductor memory device includes a sense amplification enable signal control portion which receives an initial sense amplification enable signal, sequentially delays the initial sense amplification enable signal by a plurality of predetermined time periods and selectively outputs a plurality of delayed sense amplification enable signals in view of both an operation speed and a manufacturing yield of a semiconductor memory device; a plurality of clocked sense amplifiers which each receive an output signal of the I/O sense amplifier, amplify the output signal of the I/O sense amplifier in response to each of the plurality of delayed sense amplification enable signals, and sequentially output an output signal of a power voltage level or a ground voltage level in response; and a previous-step output driving circuit which sequentially receives the output signals of the plurality of clocked sense amplifiers, delays the output signals of the plurality of clocked sense amplifiers by a predetermined time period, and then intercepts an output of the clocked sense amplifier of a previous step.