Auto-Recovery Memory Synchronization for Radiation Fault Tolerance
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Solution Overview
Problem
Existing memory controller synchronization methods in space-based or high-reliability systems using Field Programmable Gate Arrays (FPGAs) are prone to radiation effects, leading to data corruption and require additional circuitry for fault recovery, as they generate glitches and are not self-synchronizing.
Innovation Solution
The implementation of auto-recovery fault-tolerant memory synchronization using integrated majority voting circuits with separate memory address counters for write and read operations, synchronizing external and internal clock signals to minimize metastability and data loss, and employing a hold register to store the write counter value for initializing the read counter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous signaling with conditional flags (FULL, EMPTY) is used for memory controller synchronization, then data flow control is achieved, but glitches are generated and fault recovery requires additional circuitry
Solution Approach 1:
The memory controller is designed to be self-synchronizing, automatically recovering from radiation-induced faults without requiring external intervention or additional fault recovery circuitry. The system uses inherent synchronization mechanisms through shared clock signals and counter comparison to detect and recover from faults autonomously
Solution Approach 2:
The patent removes the need for complex asynchronous signaling and conditional flag generation by using synchronous operation with shared clock signals. This extraction of asynchronous complexity eliminates glitch generation while maintaining data flow control through simpler counter comparison mechanisms
2Productivity
If separate memory address counters are used for write and read operations, then data flow control is improved, but synchronization complexity increases due to potential metastability
Solution Approach 1:
The patent uses a single shared clock signal that serves multiple functions: it clocks both the write and read counters, provides the reference for comparison logic, and ensures synchronous operation across the entire memory controller. This universal clocking approach maintains productivity through separate counters while ensuring synchronization stability
Solution Approach 2:
The patent employs asymmetric counter initialization where the read counter is loaded with the write counter value at specific synchronization points. This asymmetric loading strategy, combined with continuous comparison logic, allows separate counters to maintain proper synchronization without metastability issues by ensuring the read counter never exceeds the write counter
3Reliability
If clock synchronization is implemented to minimize metastability, then synchronization stability is improved, but device complexity increases due to additional synchronization circuits
Solution Approach 1:
The synchronization mechanism is fully self-contained within the memory controller, using the shared clock signal and internal counter comparison logic to automatically detect and resolve synchronization issues. No external synchronization circuits or additional control logic are required, as the system self-regulates through inherent synchronous operation
Data Source
AI summary
Automatic fault recovery of upsets in a memory controller are provided to minimize data loss. In addition to memory control, the present invention allows for the incorporation of majority voting circuits with integrated alignment between three voted data streams. The memory array is divided into two basic components: (1) the write side (data in); and (2) the read side (data out). Each of these components has a separate memory address counter. The write counter is loaded into a holding register during a synchronization period. After determining the validity of the write cycle for fault tolerance and setting data latency for pipelining, the read counter is loaded with the write counter value. The reading of the memory array commences at the counter value that was stored in the read counter, which is the same as the original write counter value.