Transistor Off-Leakage Control via Pulse Voltage Generation
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Solution Overview
Problem
Conventional semiconductor memory devices suffer from off-leakage issues during precharge operation mode, leading to deterioration in device characteristics due to gate-induced drain leakage (GIDL) and junction leakage, which are not effectively controlled by existing methods.
Innovation Solution
A semiconductor device incorporating a pulse voltage generator that supplies pulse voltages with specific frequencies to control the channel formation of transistors, preventing GIDL by maintaining the transistor in an off state with a higher frequency pulse and switching to an on state with a lower frequency pulse, thereby minimizing potential differences and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If negative voltage is supplied to the substrate to suppress off-leakage, then threshold voltage of the transistor is increased, but junction leakage in source/drain occurs
Solution Approach 1:
The patent changes the voltage parameter applied to the gate from a static negative voltage to a dynamically varying voltage that includes a pulse component. This parameter change allows the gate voltage to modulate the channel conductivity, suppressing off-leakage while preventing the formation of large potential differences that cause GIDL.
Solution Approach 2:
The patent applies periodic pulse voltages to the gate terminal to control the transistor state. The pulse frequency is specifically chosen to be higher than the cutoff frequency of the transistor, creating periodic channel formation and suppression that effectively reduces off-leakage current while avoiding continuous large potential differences.
2Reliability
If negative voltage is supplied to the word lines to suppress off-leakage, then transistor threshold voltage is increased, but gate induced drain leakage (GIDL) occurs due to increased potential difference
Solution Approach 1:
The patent changes the gate voltage parameter from a static negative voltage to a dynamic voltage with pulse components. This allows precise control of the potential difference between gate and drain, suppressing off-leakage while preventing GIDL by avoiding large sustained potential differences.
Solution Approach 2:
Periodic pulse voltages are applied to the gate at frequencies above the transistor cutoff frequency. This periodic action creates transient channel formation that suppresses off-leakage current while the high-frequency nature of the pulses prevents the establishment of large potential differences that would cause GIDL.
3Reliability
If the transistor is kept in off state to reduce leakage, then off-leakage is suppressed, but device operational speed is reduced
Solution Approach 1:
The patent applies periodic pulse voltages at frequencies higher than the transistor cutoff frequency. This periodic action allows the transistor to rapidly switch between on and off states, maintaining low leakage during off periods while enabling fast operational response when needed, thus balancing leakage reduction with operational speed.
Solution Approach 2:
The patent introduces dynamic voltage control to the gate terminal, making the transistor state可调 (adjustable) rather than statically fixed. The dynamic pulse voltage allows the transistor to adapt between on and off states, achieving low leakage when required while maintaining operational speed capability when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents off-leakage by controlling the channel formation of transistors, improving device characteristics and reducing GIDL, while also simplifying manufacturing processes and enhancing operational speed.
Implementation Method 1
Conventional semiconductor memory devices suffer from off-leakage issues during precharge operation mode, leading to deterioration in device characteristics due to gate-induced drain leakage (GIDL) and junction leakage
Data Source
AI summary
Semiconductor device capable of preventing off-leakage of the transistor may include a pulse voltage generator configured to generate a pulse voltage, and a transistor configured to have a gate provided with the pulse voltage. The transistor is in an off state in response to the pulse voltage.