Cu Power Terminal Bonding Structure for Void-Resistant Semiconductor Packaging
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Solution Overview
Problem
Existing semiconductor device manufacturing methods face challenges in bonding external terminals and circuit patterns without causing damage, chipping, or short circuits, particularly when using ultrasonic bonding, and sintering processes can lead to uneven particle density and void formation.
Innovation Solution
The use of pressureless Cu paste for bonding, combined with a penetrating portion in the bond portion and a skirt-shaped Cu sintered material, allows for load-free bonding and uniform sintering, enhancing bonding strength and reducing void ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If ultrasonic bonding is used to bond external terminals and circuit patterns, then bonding can be achieved, but damage, chipping, or short circuits may occur
Solution Approach 1:
A bonding material is introduced as an intermediary substance between the external terminal and the circuit pattern. This bonding material absorbs the mechanical stress and energy during bonding, preventing direct contact damage between the terminal and pattern. The bonding material acts as a cushioning layer that enables reliable bonding without causing chipping or short circuits to the delicate circuit pattern.
2Strength
If sintering process is used for bonding, then bonding strength is improved, but uneven particle density and void formation occur
Solution Approach 1:
The bonding material is designed with spatially varying properties to address different regions' requirements. The particle size distribution, composition, or density of the bonding material is optimized locally - finer particles in regions requiring dense filling, coarser particles in regions needing stress distribution. This local quality variation ensures uniform particle density throughout the sintered bond while maintaining high bonding strength.
3Reliability
If load is applied during bonding, then bonding reliability is improved, but the circuit pattern and external terminal may be damaged
Solution Approach 1:
The bonding material is pre-applied to the bonding surface before the bonding process begins. This pre-applied layer serves as a cushioning barrier that protects both the circuit pattern and external terminal from direct mechanical load during bonding. The bonding material deforms under load, absorbing stress and preventing damage to the bonded components while still enabling reliable bonding through its own mechanical properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures reliable and durable connections between power and signal terminals and circuit patterns, minimizing damage and improving electrical properties and shear strength.
Implementation Method 1
the bond portion and the circuit pattern are bonded by a bonding material containing particles of metal of a same type as the power terminal and the circuit pattern
Data Source
AI summary
A semiconductor device according to an embodiment includes an insulating board having a circuit pattern, a semiconductor chip fixed on the insulating board and electrically-connected with the circuit pattern, and a power terminal that includes metal of a same type as the circuit pattern, and is electrically-connected with the circuit pattern, in which the power terminal includes a bond portion to be bonded with the circuit pattern, the bond portion having a plate shape, a penetrating portion penetrating through the bond portion in a thickness direction of the bond portion, and an extending portion that extends upward by bending from one end portion of the bond portion, and is configured to be able to connect the circuit pattern and an external device, and the bond portion and the circuit pattern are bonded by a bonding material containing particles of metal of a same type as the power terminal and the circuit pattern.


