Current-Controlled CMOS Logic for Low-Power Stable Subthreshold Operation
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Solution Overview
Problem
Existing sub-threshold logic gates face challenges in reducing power dissipation and variability due to process variations, leading to increased complexity and power consumption, while maintaining design simplicity and robustness.
Innovation Solution
A current-controlled CMOS logic architecture, referred to as the 3C architecture, which uses a modified differential pair construct with a current controller to independently control the current through N-channel and P-channel devices, reducing the sensitivity to threshold voltages and allowing for equal p-transistor and n-transistor sizes, thereby minimizing energy use and variance in operating frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If vdd is reduced below threshold voltages to reduce power, then energy consumption decreases, but sensitivity to process variations increases greatly
Solution Approach 1:
The patent changes the operating parameters by introducing a body bias voltage (Vbb) that is different from the supply voltage (Vdd). This allows the transistors to operate in the sub-threshold region with reduced power consumption while the body bias compensates for process variations, maintaining reliability. The independent control of Vbb enables optimization of both energy consumption and process variation sensitivity.
2Reliability
If adaptive body biasing feedback scheme is implemented to control statistical variations, then immunity to process variation improves, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex feedback circuitry, delay monitor, comparator, clock, and shift register from the system. Instead of using adaptive body biasing feedback schemes, the invention uses simple independent body bias voltage control that achieves process variation immunity without the associated complexity and power overhead.
3Reliability
If transistor sizes are adjusted to reduce delay variation, then frequency stability improves, but gate area increases significantly
Solution Approach 1:
The patent changes the approach from geometric parameter adjustment (transistor sizing) to electrical parameter control (body bias voltage). By adjusting Vbb independently for n-channel and p-channel devices, the invention achieves frequency stability and process variation immunity without increasing transistor sizes or gate area.
4Reliability
If large intrinsic load (16 fF) is specified to reduce delay variance, then operating frequency stability improves, but power dissipation increases and speed decreases
Solution Approach 1:
The patent changes the approach from increasing load capacitance to controlling transistor current through independent body biasing. By adjusting Vbb for n-channel and p-channel devices separately, the invention reduces delay variance without requiring large intrinsic loads, thereby avoiding increased power dissipation and speed degradation.
Data Source
AI summary
A semiconductor building block is disclosed which includes a plurality of logic gates, each having at least one P-channel device, at least one N-channel device, and a current controller controlling current for each of the plurality of logic gate having a voltage source input (vdd), a ground input (vss), a first input current (ibiasn) adapted to control current through the at least one N-channel device, a second input current (ibiasp) adapted to control current through the at least one P-channel device, and an analog voltage input (delta) representing i) a predetermined ratio between respective on currents in the at least one P-channel device to ibiasp, and ii) the predetermined ratio between respective on currents in the at least one N-channel device to ibiasn.