Current Mirror Circuit With Capacitive Gate Boost for Fast Startup
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Solution Overview
Problem
Existing current mirror circuits have limitations in switching frequencies, leading to slow ramp-up of current during startup, which restricts the operational frequency of circuits like charge pumps.
Innovation Solution
A fast-switching current mirror circuit design that includes specific configurations of transistors, capacitors, and bias circuits to enable rapid current ramp-up and controlled current flow during startup, allowing for higher switching frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard current mirror circuit is used to limit in-rush current during startup, then current limiting is achieved, but the switching frequency is limited and current ramp-up is slow
Solution Approach 1:
The capacitor is pre-charged to a first voltage level before the current mirror is activated. When the current mirror turns on, the pre-charged capacitor provides an immediate voltage boost to the gate of the output transistor, enabling fast current ramp-up without compromising the soft-start current limiting function.
Solution Approach 2:
The circuit uses periodic switching of the current mirror with controlled duty cycle. The capacitor is periodically charged and discharged in synchronization with the switching cycle, creating a pulsed current delivery mechanism that achieves both current limiting and fast ramp-up during active periods.
2Reliability
If the top FET switch is used as a current source during startup to limit in-rush current, then soft start is achieved, but the operational frequency is restricted
Solution Approach 1:
The capacitor is pre-charged during a startup phase before the main switching operation begins. This preliminary charging action allows the FET to switch at full speed once activated, while the capacitor's stored energy provides the initial current boost needed for fast switching.
Solution Approach 2:
The circuit transitions from a static current-limiting mode during startup to a dynamic high-frequency switching mode during operation. The capacitor's voltage and the FET's operating state dynamically change over time, enabling the system to adapt between soft-start and high-speed operation.
3Speed
If a capacitor is added to provide a voltage boost for fast current ramp-up, then switching speed is improved, but circuit complexity increases
Solution Approach 1:
The added capacitor serves multiple functions: it provides voltage boost for fast current ramp-up, maintains soft-start current limiting, and enables high-frequency switching operation. By making the capacitor multi-functional, the circuit achieves performance improvements without proportionally increasing complexity.
Solution Approach 2:
The capacitor acts as an intermediary energy storage element between the power supply and the current mirror output. It mediates the transition from slow ramp-up to fast switching by providing stored energy during the critical switching transition period, reducing the burden on other circuit components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit achieves faster current ramp-up and extended current flow windows, enabling higher operational frequencies, typically two or more times faster than conventional designs, which is beneficial for applications like cellular telephones and laptop computers.
Implementation Method 1
a capacitor coupled between a control input of a fifth transistor and a node between conduction channels of the fifth and fourth transistors
Data Source
AI summary
A current mirror circuit that allows for fast ramp-up of current for an output, thereby enabling a fast-switched current source with limited current during startup. One embodiment includes first and second transistors coupled in a current mirror configuration; a third transistor including a gate configured to be coupled to an input node, and having a conduction channel coupled between a first voltage source and the gates of the first and second transistors; a fourth transistor coupled to a second voltage source and a gate configured to be coupled to the input node; a fifth transistor including a conduction channel coupled between the conduction channels of the second and fourth transistors, and a gate coupled to a bias circuit; and a capacitor coupled between the gate of the fifth transistor and the drains of the fifth and fourth transistors.