Symmetrical Current Mirror Layout for Gradient Compensation
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Solution Overview
Problem
Current semiconductor devices with current mirror circuits experience output capability variations due to gradient effects in manufacturing processes, such as angle differences in light sources and etching, leading to inconsistent circuit characteristics across different voltage-to-current converters.
Innovation Solution
A semiconductor device layout with a substrate arranged in a line-symmetrical and point-symmetrical array configuration, where first and second voltage-to-current converters are positioned to minimize gradient effects, ensuring synchronized and symmetrical sub-converter operations, thereby reducing output capability variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If all transistors of the voltage-to-current converter are aligned in a row and on the same oxide diffusion region to share the OD region, then the area utilization ratio of the semiconductor device is increased, but the gradient effect in efficiency causes different voltage-to-current converters on different rows to have different circuit characteristics and output capabilities
Solution Approach 1:
The patent applies asymmetry by intentionally introducing dummy transistors to create an asymmetric layout that compensates for the gradient effects. The dummy transistors are added to specific voltage-to-current converters based on their position in the array, creating deliberate asymmetries in the layout that counterbalance the systematic gradient variations across different rows and columns, thereby improving output capability consistency while maintaining area efficiency
Solution Approach 2:
The patent changes the layout parameters of voltage-to-current converters by adjusting the number and position of dummy transistors in different converters. This parameter adjustment compensates for gradient effects by modifying the effective area and configuration of transistors in specific locations, ensuring that converters experiencing stronger gradient effects have compensatory dummy transistors to maintain uniform output characteristics
2Productivity
If transistors are arranged to share oxide diffusion regions to reduce total layout area, then manufacturing density is improved, but gradient effects from light source angle differences and etching variations cause inconsistent circuit characteristics
Solution Approach 1:
The patent applies local quality by introducing dummy transistors specifically to voltage-to-current converters that are more affected by gradient effects based on their position in the array. Instead of uniformly treating all converters, the layout is locally adjusted by adding dummy transistors to specific converters in specific rows and columns, creating position-dependent compensation that addresses local gradient variations while maintaining overall manufacturing density
Solution Approach 2:
The patent modifies the layout parameters of voltage-to-current converters by selectively adding dummy transistors to converters in different positions. This changes the effective transistor count and area parameters locally to compensate for gradient effects, ensuring that converters experiencing different gradient strengths have adjusted parameters that result in consistent output characteristics across the entire array
Data Source
AI summary
A semiconductor device includes a substrate, two first voltage-to-current converters and two second voltage-to-current converters. The substrate includes four layout regions arranged in an array having a plurality of columns and a plurality of rows. The array is line-symmetrical with respect to a first axis and line-symmetrical with respect to a second axis, wherein the first axis perpendicularly intersects the second axis at an array center point of the array. The two first voltage-to-current converters are respectively arranged in two of the four layout regions, wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point. The two second voltage-to-current converters are respectively arranged in the other two of the four layout regions, wherein layouts of the two second voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.