Current-Controlled Oscillator With Single-Comparator 50% Duty Cycle
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Solution Overview
Problem
Traditional current-controlled oscillators require multiple current sources and comparators, leading to high power consumption and area occupancy, and struggle to maintain a 50% duty cycle due to mismatch issues, which is inefficient for modern integrated circuit designs.
Innovation Solution
A current-controlled oscillator design utilizing a single comparator and a single current source in the frequency generation path, with identical capacitors to ensure a 50% duty cycle, reducing power consumption and area while eliminating comparator and current source mismatch issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional architecture with two current sources and two comparators is used, then the oscillator can generate clock signals, but power consumption and area occupancy increase significantly
Solution Approach 1:
The patent combines two separate current sources into a single current source that is shared by both capacitors, and merges the functionality of two comparators into a single comparator that sequentially charges both capacitors. This consolidation reduces the total component count while maintaining the oscillation function, directly addressing the contradiction between power consumption and device complexity.
Solution Approach 2:
The single current source serves dual functionality by sequentially charging both capacitors C1 and C2, and the single comparator performs multiple comparison operations across different voltage thresholds. This multi-functionality eliminates the need for dedicated components for each capacitor, reducing overall power consumption and area while preserving the dual-clock output capability.
2Area of stationary object
If traditional architecture with two comparators is used, then frequency generation is achieved, but area occupancy increases for low cost designs
Solution Approach 1:
The patent merges two comparator functions into a single comparator by implementing sequential charging of capacitors C1 and C2. The single comparator toggles between comparing Vnode1 against VREF1 and Vnode2 against VREF2 at different time intervals, achieving the same frequency generation function with reduced area occupancy.
Solution Approach 2:
The oscillator employs periodic switching between charging capacitor C1 and charging capacitor C2 through controlled switching of transistors. This periodic action allows a single comparator to service both capacitors alternately, reducing the need for two simultaneous comparators and thereby decreasing area occupancy while maintaining the required oscillation frequency.
3Use of energy by moving object
If traditional architecture with two current sources is used, then oscillation function is achieved, but current consumption increases for low power applications
Solution Approach 1:
The patent combines two separate current sources into one shared current source that alternately charges capacitors C1 and C2. This merging reduces the total current consumption because the same current flows through different capacitors at different times rather than requiring two simultaneous current paths, directly addressing the contradiction between current consumption and oscillation function.
Solution Approach 2:
The oscillator implements periodic switching between two charging paths: one through capacitor C1 and another through capacitor C2. A single current source provides current during each half-cycle, alternating between the two capacitors. This periodic action reduces current consumption compared to having two continuous current sources, while still achieving the required oscillation frequency and dual-clock output.
Data Source
AI summary
A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.