Current Sense Amplifier Initial Charging Circuit
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Solution Overview
Problem
The current sense amplifier in semiconductor memory devices, particularly of the current sense type, faces challenges with high power consumption due to excessive initial current during bit line charging, which affects data sensing accuracy and efficiency, especially in advanced fine patterning devices with larger bit line capacities.
Innovation Solution
A semiconductor memory device with a current sense type sense amplifier that includes an initial charging circuit capable of suppressing current only during a certain starting period, using a current control circuit to restrict initial charging current and a power circuit to provide a lower supply voltage for initial charging, allowing direct power source connection for subsequent periods to prevent excessive initial current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the current sense type sense amplifier directly connects the power source to charge the bit line, then the charging speed is improved, but excessive initial current flows causing high power consumption
Solution Approach 1:
The patent applies preliminary action by introducing a current control circuit that pre-regulates the charging current before it reaches the bit line. The current control circuit is activated first to establish current limits, then the power source is connected, ensuring that excessive initial current is prevented from flowing while still enabling fast charging through direct power source connection.
Solution Approach 2:
The current control circuit serves as an intermediary between the power source and the bit line. It mediates the charging process by controlling the current flow, allowing the system to benefit from direct power source connection for speed while preventing excessive initial current through current regulation.
2Use of energy by moving object
If the current sense type sense amplifier uses a current control circuit to restrict current, then power consumption is reduced, but the bit line current cannot be determined from the threshold of a cell transistor when current flows in all bit lines
Solution Approach 1:
The patent applies segmentation by dividing the charging process into distinct phases: an initial charging phase where the current control circuit is active to restrict current and reduce power consumption, and a sensing phase where the bit line is isolated from the current source load. This temporal segmentation allows current restriction during charging while preserving sensing accuracy when needed.
Solution Approach 2:
The system dynamically switches between different operational modes. The current control circuit is activated during charging phases and deactivated or isolated during sensing phases. The bit line connection to the current source load is dynamically controlled, allowing the system to adapt its current control characteristics based on the operational phase.
3Adaptability or versatility
If the bit line capacity is increased in advanced fine patterning devices, then the memory device capability is improved, but charging the bit line consumes a larger amount of current
Solution Approach 1:
The current control circuit implements feedback control to monitor and regulate the bit line charging current. By continuously monitoring the current flow and adjusting control signals accordingly, the system can charge larger capacity bit lines while maintaining current within acceptable limits, thus supporting advanced fine patterning devices without excessive power consumption.
Data Source
AI summary
A semiconductor memory device comprises a plurality of memory cells connected to a bit line, and a sense amplifier of the current sense type. The sense amplifier includes an initial charging circuit capable of initially charging the bit line with a suppressed value of current only for a certain starting period during an initial charging period. The sense amplifier detects a value of current flowing in the bit line to decide data read out of each of the memory cells.