Curved Partition Power Chip Layout for Low-Inductance Bridge Circuits
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Solution Overview
Problem
The increasing demand for high power density and efficiency in data processing centers is hindered by parasitic inductance in existing power chips, which leads to higher energy consumption and larger footprints due to the inefficiencies in commutation circuit loops, particularly at higher frequencies.
Innovation Solution
A power chip design featuring multiple partitions arranged alternately along a curve, with integrated capacitors and driving circuits, reduces the distance between geometrical centers of partitions and capacitors, thereby minimizing the area of the commutation circuit loop and decreasing parasitic inductance, enhancing efficiency and power density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power switches are arranged in conventional layouts, then device complexity is reduced, but parasitic inductance increases leading to higher energy consumption
Solution Approach 1:
The power chip is divided into multiple first partitions and second partitions, each containing power switches. These partitions are arranged alternately along a curve to minimize the area of the commutation circuit loop, thereby reducing parasitic inductance and energy loss.
Solution Approach 2:
The partitions are arranged along a curved path rather than a straight line. This curved arrangement allows the power switches to be positioned in a compact configuration that minimizes the commutation loop area while maintaining electrical connectivity, thus reducing parasitic inductance.
2Ease of manufacture
If partition distance is increased, then manufacturing is easier, but commutation circuit loop area increases leading to higher parasitic inductance
Solution Approach 1:
The distance between adjacent partitions is optimized to a specific range that balances manufacturing feasibility with electrical performance. This parameter optimization ensures that the partitions are close enough to minimize loop area but far enough to allow proper fabrication processes.
3Power
If power density is increased, then energy efficiency improves, but voltage spikes increase due to parasitic inductance
Solution Approach 1:
By segmenting the power chip into multiple small partitions arranged alternately, the commutation loop area is minimized. This segmentation allows higher power density while keeping parasitic inductance low, thereby reducing voltage spikes during switching operations.
4Productivity
If switching frequency is increased, then processing efficiency improves, but switching losses increase due to parasitic inductance
Solution Approach 1:
The curved arrangement of partitions enables compact positioning of power switches, minimizing the commutation loop area. This allows the system to operate at higher switching frequencies with reduced parasitic inductance, thereby maintaining low switching losses while improving processing efficiency.
Data Source
AI summary
A power chip, includes a metal region; a wafer region. The wafer region includes at least one first partition, forming a first power switch; and at least one second partition, forming a second power switch. The first power switch and the second power switch are electrically connected, a total number of the at least one first partition and the at least one second partition is not less than 3, and the at least one first partition and the at least one second partition are disposed alternatively along a curve.