Melt-Annealed Source/Drain Regions With Curved Silicide Interface
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Solution Overview
Problem
In the formation of Fin Field-Effect Transistors (FinFETs), the existing anneal processes do not effectively reduce contact resistance between source/drain regions and overlying silicide regions, leading to suboptimal performance due to planar interfaces.
Innovation Solution
The use of a melt anneal process, where at least some portions of the source/drain regions are molten, resulting in a curved interface with the silicide regions, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional anneal processes are used to form source/drain silicide regions, then the process is simple and straightforward, but contact resistance between source/drain regions and silicide regions remains high due to planar interfaces
Solution Approach 1:
The patent employs a melt anneal process where the source/drain regions are heated to melt and then rapidly cooled, creating a curved interface between the source/drain regions and silicide regions. This phase transition (solid-liquid-solid) transforms the原本 planar interface into a curved one, which increases the contact area and reduces contact resistance between the source/drain regions and silicide regions.
Solution Approach 2:
The patent changes the temperature parameter during the anneal process, heating the source/drain regions to a temperature above their melting point and then rapidly cooling them. This parameter change (temperature control) enables the formation of a curved interface that improves electrical contact while managing the complexity through controlled thermal processing.
2Reliability
If higher boron concentration is introduced to improve short-channel effect and DIBL performance, then device performance improves, but impurity diffusion increases in non-molten regions
Solution Approach 1:
The melt anneal process uses phase transition to control impurity distribution. During melting and rapid cooling, boron atoms are redistributed within the molten region, achieving high concentration where needed for short-channel effect and DIBL improvement. The rapid solidification freezes this desired distribution, preventing further diffusion and stabilizing the impurity profile.
Solution Approach 2:
The patent uses rapid thermal processing to skip through the temperature range where unwanted diffusion would occur. By quickly heating to the melting point and then rapidly cooling, the process achieves boron redistribution and concentration enhancement without allowing excessive diffusion in non-molten regions, thus improving performance while controlling impurity stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The melt anneal process achieves reduced contact resistance and improved performance by allowing for higher boron concentration and redistribution of germanium, enhancing short-channel effect and Drain Induced Barrier Lowering (DIBL) performance while minimizing impurity diffusion in non-molten regions.
Implementation Method 1
performing a melt anneal on the semiconductor region, wherein at least a portion of the semiconductor region is molten during the melt anneal
Implementation Method 2
redistribution of germanium, enhancing short-channel effect and Drain Induced Barrier Lowering (DIBL) performance
Data Source
AI summary
A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.