Curved Surface Dielectric Patterns for Mold Electronics Stress Management
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Solution Overview
Problem
Mold electronics technology faces challenges with circuit delamination or breakage due to deformation and stress, especially in complex multi-layer circuit designs, which affects the reliability of electronic devices.
Innovation Solution
The electronic device incorporates a surface structure with a substrate, conductive lines, and dielectric patterns. The dielectric patterns have varying widths based on the tensile rate, and the thickness ratio of the dielectric patterns to the conductive lines is controlled, or the routing direction of the conductive lines is aligned differently from the tensile direction, to alleviate deformation stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If mold electronics technology is used to integrate electronic circuits with curved surfaces, then circuit layout flexibility is improved, but circuit reliability deteriorates due to delamination or breakage from deformation and stress
Solution Approach 1:
The dielectric layer is designed with varying thickness across different regions: thicker in high-stress areas (convex portions, bending zones) and thinner in low-stress areas. This local variation in dielectric thickness provides enhanced stress buffering where needed while maintaining circuit functionality throughout, directly resolving the contradiction between layout flexibility and circuit reliability
Solution Approach 2:
The patent changes the physical parameter of dielectric layer thickness from uniform to non-uniform distribution. By adjusting the thickness parameter spatially according to stress distribution patterns, the design accommodates curved surface deformation while protecting conductive lines from stress-induced damage, thus improving reliability without sacrificing layout adaptability
2Adaptability or versatility
If multi-layer circuit stack design is implemented to cope with diverse applications, then application versatility is improved, but circuit reliability deteriorates due to increased likelihood of abnormalities
Solution Approach 1:
In multi-layer circuit designs, the dielectric layer thickness is locally increased in regions where conductive lines from different layers interact or where stress concentration occurs. This targeted thickening provides enhanced protection at critical interfaces while maintaining the complexity benefits of multi-layer design for diverse applications
Solution Approach 2:
The patent employs a composite structure combining conductive lines, varied-thickness dielectric layers, and protective coatings. This composite approach allows the circuit stack to handle diverse applications while the dielectric variation provides stress management across layers, preventing delamination and maintaining reliability despite increased structural complexity
3Ease of manufacture
If uniform dielectric layer is used over conductive lines, then manufacturing simplicity is improved, but stress buffering capability deteriorates
Solution Approach 1:
The dielectric layer transitions from uniform to non-uniform thickness design. By making the thickness a local property based on stress requirements, the manufacturing process becomes more complex but provides significantly enhanced stress buffering capability in critical regions, justifying the increased manufacturing sophistication
Solution Approach 2:
The dielectric layer thickness is predetermined and designed before final circuit assembly, with thicker regions pre-positioned in high-stress areas. This preliminary design approach allows stress buffering to be built into the structure proactively, preventing damage before it occurs rather than reacting to stress issues after manufacturing
Data Source
AI summary
An electronic device includes a surface structure. The surface structure has a curved surface and includes a substrate, a first conductive line, and a first dielectric pattern. The first conductive line is disposed above the substrate. The first dielectric pattern is disposed above the first conductive line and overlaps with the first conductive line. The surface structure has a first region and a second region. The first dielectric pattern in the first region has a first average width, the first dielectric pattern in the second region has a second average width, and the first average width is different from the second average width.