Cut-In Voltage Test Method Using Two-Step Scanning

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Solution Overview

Problem

Current test methods for cut-in voltage in semiconductor products face challenges in achieving high accuracy and efficiency, particularly in mismatch tests, due to limitations in scanning step length, which affects test results and efficiency.

Innovation Solution

A two-step method involving coarse and accurate scanning, where the scanning step length is progressively shortened until it reaches a preset threshold, allowing for precise determination of cut-in voltage by adjusting the gate electrode voltage and measuring drain electrode current, ensuring the current exceeds or falls below a target value.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a large scanning step length is used for cut-in voltage measurement, then test efficiency is improved, but test accuracy is significantly degraded

Engineering Contradiction:
Improvetest efficiencyVSAvoidcut-in voltage measurement accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent divides the voltage scanning process into multiple segments: a first scanning range with a first scanning step length, and a second scanning range with a second scanning step length that is smaller than the first. This segmentation allows the system to efficiently cover a broad voltage range initially, then focus on the critical region around the cut-in voltage with finer resolution, thereby resolving the contradiction between test efficiency and measurement accuracy.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If a small scanning step length is used for cut-in voltage measurement, then test accuracy is improved, but test efficiency is significantly degraded

Engineering Contradiction:
Improvecut-in voltage measurement accuracyVSAvoidtest efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent divides the voltage scanning process into multiple segments: a first scanning range with a first scanning step length, and a second scanning range with a second scanning step length that is smaller than the first. This segmentation allows the system to efficiently cover a broad voltage range initially, then focus on the critical region around the cut-in voltage with finer resolution, thereby resolving the contradiction between test efficiency and measurement accuracy.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If single-pass scanning is used for cut-in voltage test, then test process is simple, but cannot meet both accuracy and efficiency requirements of mismatch test

Engineering Contradiction:
Improvetest process complexityVSAvoidmismatch test accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent divides the voltage scanning process into multiple segments: a first scanning range with a first scanning step length, and a second scanning range with a second scanning step length that is smaller than the first. This segmentation allows the system to efficiently cover a broad voltage range initially, then focus on the critical region around the cut-in voltage with finer resolution, thereby resolving the contradiction between test efficiency and measurement accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs a preliminary coarse scanning operation first to identify the approximate location of the cut-in voltage, then uses this information to guide a subsequent fine scanning operation in the critical region. This preliminary action eliminates the need for exhaustive fine scanning across the entire voltage range, thereby achieving high accuracy without excessive complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9696371B2Test method and system for cut-in voltage
Publication Date: 2017.07.04 CSMC TECH FAB2 CO LTD
  • US9696371B2 patent drawing
  • US9696371B2 patent drawing
  • US9696371B2 patent drawing

AI summary

A test method and system for cut-in voltage. The method comprises: coarse scanning of the cut-in voltage: a grid voltage, i.e., the cut-in voltage, is quickly determined when a drain terminal current is greater than a target current for the first time (100); accurate scanning of the cut-in voltage: a scanning step length is shortened continuously until the scanning step length is shorter than a preset step length, and each time the scanning step length is shortened, the scanning is conducted according to the current shortened scanning step length on the basis of the cut-in voltage determined in the former time, and then the cut-in voltage under the condition of the current shortened scanning step length is determined again (200). The scanning voltage is automatically increased or decreased by the test method and system through adding high resolution and high precision test conversion into a second scanning test, and therefore the testing of the cut-in voltage becomes more efficient and more accurate.