Cut Pattern Modification for IC Manufacturability

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Solution Overview

Problem

Current mandrel-cut double patterning techniques for semiconductor integrated circuits (ICs) face challenges due to complicated pattern layouts and narrow end-to-end spaces between patterns, making mask and wafer fabrication difficult, particularly for FinFETs, which can lead to issues like pattern shorting and increased manufacturing complexity.

Innovation Solution

The method involves modifying cut patterns by splitting them into subsets for separate masks, replacing elongated patterns with smaller or square patterns, and adjusting cut layers to avoid overlapping with via features, thereby increasing spacing and reducing pattern length, which enhances manufacturability and the photolithography process window.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If mandrel-cut double patterning technique is used to fabricate high density IC devices, then photolithographic process window is improved, but pattern layout becomes complicated and end-to-end spaces between patterns become narrow

Engineering Contradiction:
Improvephotolithographic process windowVSAvoidpattern layout complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The cut pattern is divided into multiple subsets (first subset and second subset) that are formed by separate masks. This segmentation allows each subset to have simpler, more manufacturable patterns while collectively achieving the desired cut functionality, thereby resolving the contradiction between manufacturing precision and layout complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension by using multiple mask layers (first mask and second mask) to form different subsets of the cut pattern. Instead of attempting to form all cut patterns in a single layer, the solution distributes patterns across multiple layers, simplifying each individual layer's pattern complexity while maintaining overall manufacturing precision

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If cut pattern design is optimized for density, then manufacturing efficiency is improved, but end-to-end spaces between patterns become narrow causing fabrication difficulties

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidmask and wafer fabrication ease
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

By segmenting the cut pattern into multiple subsets formed by different masks, the patent allows each subset to have adequate spacing for easy fabrication. The segmentation maintains manufacturing efficiency through optimized pattern distribution while ensuring each individual pattern subset meets minimum spacing requirements for ease of manufacture

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different pattern densities and spacing characteristics to different regions and subsets of the cut pattern. Each mask layer can be optimized with appropriate local spacing and pattern density, allowing high overall manufacturing efficiency while maintaining adequate local spaces for easy mask and wafer fabrication

Inventive Principle:
Principle #3Local quality

3Productivity

If pattern density is increased for higher IC density, then production efficiency is improved, but pattern shorting risk increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidpattern shorting prevention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The cut pattern is segmented into multiple subsets formed by separate masks, which allows better control over spacing and reduces the risk of pattern shorting. This segmentation enables higher overall pattern density while maintaining adequate clearance between individual patterns through the multi-layer approach

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By distributing cut patterns across multiple mask layers (adding a vertical dimension), the patent achieves higher effective pattern density on the wafer while maintaining adequate horizontal spacing between patterns on each individual layer, thereby preventing pattern shorting while improving production efficiency

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11392745B2Method for improving circuit layout for manufacturability
Publication Date: 2022.07.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11392745B2 patent drawing
  • US11392745B2 patent drawing
  • US11392745B2 patent drawing

AI summary

A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.