CXL.mem Unordered DMA with Back Invalidate for Lower Latency

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Solution Overview

Problem

Existing unordered input/output (UIO) direct memory access (DMA) operations at Compute Express Link (CXL.mem) devices are inefficient, impacting the performance of PCIe and CXL.mem devices during data transfer operations.

Innovation Solution

Implementing mechanisms for unordered input/output direct memory access operations involving a hardware processor that issues back invalidate snoop requests to a cache coherency control unit and subsequent UIO DMA requests to a CXL.mem device, allowing for parallel processing of cache line management and data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional ordered DMA operations are used to ensure cache coherency, then data consistency is maintained, but end-to-end latency increases and performance deteriorates

Engineering Contradiction:

Improvecache coherencyVSAvoidend-to-end latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary cache line invalidation in the host processor before initiating DMA transfers. The back invalidate snoop request is issued in advance to clear cache lines, ensuring that subsequent unordered DMA operations will not encounter coherency issues. This preliminary action separates the cache management from the data transfer, allowing both to proceed efficiently without waiting for each other.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the DMA operation into two independent phases: (1) cache line invalidation handled by the back invalidate snoop request, and (2) data transfer handled by the unordered UIO DMA request. This segmentation allows the cache coherency management and data transfer to occur in parallel, eliminating the sequential dependency that causes latency in traditional ordered operations.

Inventive Principle:

Principle #1Segmentation

2Device complexity

If sequential processing of cache line management and data transfer is used, then processing simplicity is maintained, but overall throughput and productivity decrease

Engineering Contradiction:

Improveprocessing sequenceVSAvoiddata transfer throughput

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The host processor issues the back invalidate snoop request in advance before the UIO DMA request is sent to the CXL.mem device. This preliminary cache line invalidation allows the data transfer operation to proceed without waiting for cache management to complete, thereby increasing throughput while maintaining relatively simple processing logic through the use of standardized snoop request mechanisms.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12579068B2Systems, methods, and media for unordered input/output direct memory access operations

Publication Date: 2026.03.17 SK HYNIX NAND PRODUCT SOLUTIONS CORP

AI summary

Mechanisms for unordered input/output direct memory access operations are provided, including: issuing using a hardware processor a back invalidate snoop request to a cache coherency control unit of a host processor; and issuing an unordered input/output direct memory access operation request to a Compute Express Link memory device. In some of these mechanisms, the unordered input/output direct memory access operation request is for a read operation. In some of these mechanisms, the mechanisms further comprise receiving a response to the unordered input/output direct memory access operation request including data from the Compute Express Link memory device. In some of these mechanisms, the data was updated in response to the back invalidate snoop request. In some of these mechanisms, the unordered input/output direct memory access operation request is for a write operation.