Memory Adressing/Allocation/Relocation TRIZ Cases
- SSD Decommissioning via OTP-Grounded High-Voltage Disablement
OTP-triggered grounding disables the SSD high-voltage generator and flash interfaces, making stored data permanently inaccessible with low power use.
- GC-Aware Resource Allocation for Containerized Applications
eBPF-based tracing captures garbage collection calls and resource usage to guide autoscaling and reduce GC-driven cloud application slowdowns.
- Mirrored Write Cache Sizing Based on Battery Charge Level
Battery charge monitoring adjusts mirrored write cache size so only vaultable data is buffered during outages, reducing loss risk.
- Program Object Caching with Reusable Preload State
Cache object information is saved at program closure and reused at startup to avoid manual preload policies, misloading, and extra compute.
- NAND Memory Slice Programming with Continuous Voltage Sequencing
Sequential select-line activation lets multiple NAND memory slices share one programming cycle, cutting voltage ramp transitions and programming time.
- Fungible Memory Allocation Across PFEs for Dynamic Packet Processing
A shared controller allocates fungible memory across PFEs for ingress and egress workloads, improving utilization in dynamic SDN traffic.
- Memory Controller Sub-Queue Arbitration for Faster DDR Command Selection
Multiple command sub-queues with dedicated arbiters cut DDR timing evaluation delays and speed memory access request selection.
- CXL SSD Memory Service Partitioning for Power-Fail Data Integrity
A CXL SSD partitions volatile and non-volatile memory so hosts can configure fast memory services without sacrificing power-fail data integrity.
- Data Memory Extraction Strategy for Low-Latency Production Control
Dynamic filtering, standardization, and time-sliced extraction cut resource use and latency when retrieving production control data.
- Staggered Memory Row Access for Lower Peak Current
Sequential row-segment activation spreads memory bank current over time, cutting power peaks and EMI in low-power operation.
- Storage Block Traversal Authentication for Host Access Control
Iterative block reading lets a storage device continuously verify the host and update access permissions with low complexity.
- On-Chip Data Buffering for Stalled Network Returns
Auxiliary memory control detects stalled on-chip data and moves it into selected local storage sectors to prevent network-wide stalls.
- Sparse Memory Access Control for Low-Power Read and Write Bypass
Address matching halts reads and writes to sparse-data locations, cutting memory power dissipation and avoiding unnecessary bank access.
- Multiplexed Memory Access for Continuous Random Column Reads
Continuous random-column access keeps a shared row active to remove tCPH delay and speed multiplexed memory reads and writes.
- SSD Multi-Bit Cell Storage Modes for Data Retention After EOL
Adjustable threshold-voltage widths let SSDs store critical data in high-quality areas to preserve readability after power loss and EOL.
- CXL Memory Data Redistribution for Lower Access Latency
Usage-ratio thresholds shift data from overloaded CXL memory to shared memory, reducing skew and access latency across devices.
- Disaggregated Memory Architecture With Photonic Interconnects
Photonic links connect disaggregated memory and compute to deliver unified high-bandwidth access with lower power and fewer bottlenecks.
- M_CAN Controller Initialization for Full CAN-FD Without a Microprocessor
A hardware host preloads CAN registers and filters so simple nodes can join full CAN/CAN-FD buses without a gateway or microprocessor.
- On-Chip Interconnect for Load-Balanced Memory Channel Access
A crossbar OCI lets each channel controller reach any memory channel, reducing load imbalance and data access delays in ML chips.
- Configuration Cache Access for Low-Latency Transaction Control
Direct cache location access lets transaction circuitry fetch configuration data without temporary storage, cutting latency, area, and power.
- Memory Card Write Protection Across Driver Protocol Switching
A first driver saves SD card lock status before protocol switching, letting the OS keep write protection when the newer driver cannot detect it.
- DDR Memory DQS Duty Cycle Adjustment for PVT-Stable Write Training
Adjustment codes tune DDR DQS duty cycle during write training to maintain accurate data transfer across PVT variations.
- Unified Memory Controller for Main Storage and Built-In EEPROM
A single controller handles main storage, built-in EEPROM, and self-test to cut chip area, logic gates, and power use.