Staggered Memory Row Access for Lower Peak Current

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Solution Overview

Problem

Existing memory devices face challenges in reducing peak current and power consumption, particularly in battery-powered systems, while minimizing electromagnetic interference.

Innovation Solution

Implementing staggered access to row segments within a memory bank by sequentially activating local wordlines and column operations with a predefined stagger interval, allowing for independent control of local wordlines and column select lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If simultaneous access to all row segments is enabled, then access speed is improved, but peak current consumption increases

Engineering Contradiction:
Improveaccess speedVSAvoidpeak current consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The row access operation is segmented into multiple independent row segment operations that can be executed sequentially with staggered timing. Each row segment is activated and accessed separately rather than simultaneously, distributing the current demand over time while maintaining functional completeness of the access operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements periodic activation of row segments with staggered intervals between segments. This periodic action allows the memory device to control peak current by spacing out activation events, while still providing timely access to all required data through the segmented periodic operations.

Inventive Principle:
Principle #19Periodic action

2Speed

If simultaneous activation of all local wordlines is performed, then operation speed is improved, but stress on electronic components increases

Engineering Contradiction:
Improveoperation speedVSAvoidstress on electronic components
Core Design Contradiction:
SpeedVSStress or pressure

Solution Approach 1:

The activation of local wordlines is divided into segmented operations where each local wordline is activated separately with staggered timing. This segmentation reduces the simultaneous switching activity and associated stress on power delivery networks and electronic components while preserving the overall operation speed through efficient sequencing.

Inventive Principle:
Principle #1Segmentation

3Productivity

If simultaneous column operations across all segments are initiated, then productivity is improved, but electromagnetic interference increases

Engineering Contradiction:
ImproveproductivityVSAvoidelectromagnetic interference
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

Column operations are segmented and executed in a staggered manner across different row segments. This segmentation reduces simultaneous switching activity and associated electromagnetic interference while maintaining productivity through efficient use of memory resources and pipelined operation sequences.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces staggered timing intervals as an intermediary mechanism between simultaneous column operations. This timing intermediary distributes electromagnetic emissions over time, reducing peak interference levels while still enabling high productivity through the coordinated sequencing of segmented operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12625799B2Memory device with staggered access
Publication Date: 2026.05.12 RAMBUS INC
  • US12625799B2 patent drawing
  • US12625799B2 patent drawing
  • US12625799B2 patent drawing

AI summary

A memory device supports low power operation by facilitating staggered access to row segments within a row of a memory bank. Upon receiving an activate command to activate a row, the memory device sequentially activates a plurality of local wordlines associated with the row with a stagger interval between activations. Upon receiving an access command associated with the activated row, the memory device sequentially initiates column operations for respective row segments with the same stagger interval between the column operations. The memory device may furthermore facilitate error correction code operations in a staggered manner by sequentially performing computations associated with the different row segments.