Unified Memory Controller for Main Storage and Built-In EEPROM
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Solution Overview
Problem
Current storage architectures in processors that use separate program memory and EEPROMs result in higher costs, increased chip area, and higher power consumption due to separate controller designs and logic gates.
Innovation Solution
A memory control system with a built-in EEPROM and a unified storage controller that integrates a control register bank, state machine, time sequence control unit, and data address processing unit, allowing for simplified read-write operations and self-testing through a test control signal, eliminating the need for a separate RAM and reducing the number of logic gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate program memory and EEPROM are used with separate controllers, then functionality is achieved, but cost increases
Solution Approach 1:
The patent combines separate program memory and EEPROM into a unified memory structure with a single controller. The controller integrates both read operations for program memory and write operations for EEPROM through a unified control unit, eliminating the need for separate controllers and reducing overall system cost while maintaining full functionality.
Solution Approach 2:
The unified controller is designed to perform multiple functions: it controls both program reading from memory and program writing to EEPROM, manages test modes, and handles configuration operations. This multi-functional approach replaces what would traditionally require separate dedicated controllers, reducing component count and cost.
2Reliability
If separate controllers are designed for program memory and EEPROM, then specialized control is achieved, but chip area increases
Solution Approach 1:
The patent merges the control functions for program memory and EEPROM into a single controller unit. The integrated controller shares common resources including the state machine, time sequence control unit, and data address processing unit, significantly reducing the chip area compared to having separate dedicated controllers for each memory type.
Solution Approach 2:
The unified controller is designed as a multi-functional unit that handles both program reading and EEPROM writing operations through a single state machine and control logic. This universal controller performs specialized control functions for different memory operations without requiring separate dedicated control circuits, thereby minimizing chip area.
3Reliability
If separate controllers are designed for program memory and EEPROM, then dedicated control logic is achieved, but number of logic gates increases
Solution Approach 1:
The patent combines the control logic for program memory and EEPROM into a single integrated controller. The unified state machine and time sequence control unit manage both memory types through shared logic gates, reducing the total number of logic gates required compared to separate dedicated control logic for each memory type.
Solution Approach 2:
The unified controller implements multi-functional control logic that handles program reading, EEPROM writing, and test operations through a single set of logic gates. The state machine and time sequence control unit perform dedicated control functions for different operations using shared logical resources, thereby reducing the overall number of logic gates while maintaining reliable specialized control.
4Reliability
If separate controllers are designed for program memory and EEPROM, then specialized control functions are achieved, but power consumption increases
Solution Approach 1:
The patent merges the control functions for program memory and EEPROM into a single controller unit. The integrated controller shares common power consumption across unified control circuits, state machine, and time sequence control unit, reducing total power consumption compared to having separate dedicated controllers that would each require independent power supply and control logic.
Solution Approach 2:
The unified controller performs specialized control functions for program reading and EEPROM writing through a single multi-functional unit. By sharing common control logic, state machine, and timing generation resources, the system achieves specialized control capabilities while minimizing power consumption through reduced circuit complexity and fewer active components.
Data Source
AI summary
A memory control system includes: a memory having a main storage module and a built-in EEPROM; a storage controller which, in a normal mode, reads a program in the main storage module on the basis of an instruction of a processor and performs read-write control on the built-in EEPROM, and in a test mode, performs read-write control on the main storage module or the built-in EEPROM on the basis of configuration of a test control signal, or completes a self-test on the basis of an instruction of the test control signal; and the processor. According to the present disclosure, resource consumption is greatly reduced; logic of a hardware control reading part after dormancy is omitted and the time consumed during dormancy and wake-up is reduced; and only one counter and one time sequence control unit are used to implement control of the time sequence of the whole system.