NAND Memory Slice Programming with Continuous Voltage Sequencing
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Solution Overview
Problem
Existing NAND flash memory programming methods are inefficient due to the time-consuming ramp-up and ramp-down of program and verification voltages across multiple memory cell slices, prolonging the programming process.
Innovation Solution
A method that continuously programs and verifies multiple memory cell slices in a single programming cycle by applying program and verification voltages sequentially to select lines and word lines, reducing the need for multiple ramp-up and ramp-down cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional sequential programming method is used for multiple memory cell slices, then programming can be completed with simple control logic, but programming time increases due to multiple voltage ramp-ups and ramp-downs
Solution Approach 1:
The patent combines the programming operations of multiple memory cell slices into a single parallel operation. By applying program voltages to first and second word lines simultaneously while using a shared select line for both memory cell slices, the method eliminates the need for sequential voltage ramp-ups and ramp-downs, thereby reducing programming time without requiring significantly more complex control logic.
2Productivity
If parallel programming of multiple memory cell slices is implemented, then programming speed increases, but control logic and voltage management complexity increases
Solution Approach 1:
The patent employs a shared select line that serves multiple memory cell slices simultaneously, allowing a single control signal to activate or deactivate programming operations across different slices. This multi-functional approach enables parallel programming while keeping the control logic relatively simple, as the same select line and control mechanisms are reused across multiple slices rather than requiring dedicated control circuits for each slice.
Solution Approach 2:
The method applies pass voltages to non-selected word lines before the actual programming operation begins. This preliminary action prepares the memory cells that will not be programmed during the current operation, preventing unwanted programming effects while the main programming proceeds in parallel on selected word lines, thus managing voltage complexity proactively.
3Reliability
If sequential select line activation is used for different memory cell slices, then interference between slices is minimized, but programming time increases
Solution Approach 1:
The patent applies different voltage levels to different word lines and select lines within the same parallel programming operation. By applying program voltages to specific word lines (first and second word lines) while applying different pass voltages to other word lines, and by selectively activating select lines for different memory cell slices, the method creates locally optimized voltage conditions that prevent interference between slices while maintaining parallel operation.
Data Source
AI summary
A programming method includes applying a program voltage to a first word line coupled to a plurality of memory cells of a first memory cell slice and a plurality of memory cells of a second memory cell slice; and during a stage of applying the program voltage to the first word line, applying a turn-on voltage to a first select line and a second select line sequentially, wherein the first select line is coupled to a select transistor of the first memory cell slice, and the second select line is coupled to a select transistor of the second memory cell slice.