Multiplexed Memory Access for Continuous Random Column Reads
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Solution Overview
Problem
Existing memory access methods, particularly in PSRAM, suffer from inefficiencies due to the need to wait for preparation times (tCPH) between consecutive access operations, which hinder faster access speeds.
Innovation Solution
Implementing random column and row access modes that allow continuous read/write operations with shared row addresses, eliminating the tCPH time by performing parallel processing of subsequent access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional memory access methods are used with word line deactivation/reactivation, then memory operations can be performed sequentially, but access speed is reduced and latency is increased due to tCPH time requirements
Solution Approach 1:
The patent applies preliminary action by keeping the word line activated in advance and maintaining it in a ready state before subsequent column address accesses are needed. This eliminates the need for repeated deactivation and reactivation cycles, allowing the memory system to be prepared for quick access without incurring tCPH delays for each operation.
Solution Approach 2:
The patent implements continuity of useful action by maintaining the word line in a continuously activated state during sequential column address accesses. This eliminates idle periods where the word line would otherwise be deactivated and/reactivated, ensuring that the memory access operation continues without interruption and without losing the tCPH time interval.
2Productivity
If word line deactivation and reactivation is performed between accesses, then memory can handle sequential operations, but the interval between accesses is increased due to tCPH time requirements
Solution Approach 1:
The memory system performs preliminary action by pre-activating and maintaining the word line in a ready state before subsequent column accesses are required. This preparation in advance eliminates the need for repeated activation cycles, allowing the system to process multiple column addresses continuously without the tCPH interval that would otherwise be required between each access operation.
Solution Approach 2:
The patent achieves continuity of useful action by keeping the word line activated throughout the sequence of column address accesses. This continuous activation removes the idle periods and tCPH delays that would normally occur between accesses, thereby increasing the overall productivity and reducing the duration of the access interval.
3Speed
If random column access mode is implemented with continuous read/write operations, then access speed is improved, but the complexity of managing shared row addresses and multiple column addresses increases
Solution Approach 1:
The patent applies segmentation by dividing the address management into distinct components: a shared row address portion that remains constant and multiple column address portions that vary. This segmentation allows the row address to be established once and reused, while only the column addresses need to be sequentially processed, thereby reducing overall address management complexity while maintaining high access speed.
Solution Approach 2:
The patent implements universality by designing the row address as a shared resource that can be reused across multiple column address accesses. This multi-functional approach allows the same row address to serve multiple purposes and multiple column accesses, reducing the need for separate address management mechanisms and simplifying the overall system while enabling continuous high-speed operations.
Data Source
AI summary
Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified random-column-access mode, in which the memory array can be continuously read or written in response to receiving multiple access addresses having a same row address and random column addresses; receiving a common row address and at least one column address via the data/address multiplexing line; outputting data read in response to the received access address via the data/address multiplexing line in the case where the mode indicates read operation, or receiving data to be written in response to the received access address via the data/address multiplexing line in the case where the mode indicates write operation; and ending the random column access mode by receiving an invalid chip-enable-signal.