DDR Memory DQS Duty Cycle Adjustment for PVT-Stable Write Training
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Solution Overview
Problem
The increasing performance requirements for Double Data Rate (DDR) random access memory are not met by current duty cycle adjustments of data strobe (DQS) signals, leading to inefficiencies in data transmission due to variations in duty cycle with Process, Voltage, and Temperature (PVT).
Innovation Solution
A method for adjusting the duty cycle of DQS signals using Write Duty Cycle Adjustment (WDCA) by configuring adjustment codes, determining correct data reading, and selecting a target adjustment code to stabilize the DQS signal within PVT variations, supported by the ONFI protocol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the duty cycle of DQS signal is adjusted to meet performance requirements, then data transmission accuracy is improved, but the system becomes more sensitive to PVT variations
Solution Approach 1:
The patent implements dynamic duty cycle adjustment by allowing the DQS signal's duty cycle to be modified in response to PVT variations. The system continuously monitors and adjusts the duty cycle parameter to maintain optimal data transmission under changing conditions, transforming a static signal into a dynamically adaptive one.
Solution Approach 2:
The patent changes the duty cycle parameter of the DQS signal to compensate for PVT variations. By adjusting this temporal parameter, the system maintains signal integrity and data transmission accuracy across different process, voltage, and temperature conditions without requiring fundamental redesign.
2Adaptability or versatility
If multiple adjustment codes are used to stabilize DQS duty cycle, then adaptability to PVT changes is improved, but device complexity increases
Solution Approach 1:
The patent segments the adjustment mechanism into discrete adjustment codes that can be independently selected and applied. Each code represents a specific duty cycle adjustment level, allowing the system to navigate through a finite set of states to achieve optimal performance without requiring complex continuous control.
Solution Approach 2:
The patent implements a feedback mechanism where the system monitors data transmission quality and uses this information to select appropriate adjustment codes. The feedback loop continuously evaluates performance and automatically selects the best adjustment code, reducing the need for manual configuration and simplifying the overall control logic.
3Reliability
If WDCA is performed multiple times with different step sizes, then data transmission reliability is improved, but time consumption increases
Solution Approach 1:
The patent applies partial adjustment action by performing WDCA multiple times with progressively smaller step sizes. Instead of exhaustive search, the system uses a hybrid approach combining automated feedback-based selection with manual intervention, achieving reliable data transmission while minimizing adjustment time through intelligent code selection.
Data Source
AI summary
Memory systems and operation methods thereof are provided. In one example, an operation method of a memory system includes: transmitting, by a memory controller of the memory system, an adjustment information; receiving, by a memory device of the memory system, the adjustment information; in response to the adjustment information, adjusting a duty cycle of data strobe (DQS) signal by the memory device; and performing a write training in accordance with an adjusted DQS signal. The adjustment information represents a step size and an adjustment direction for adjusting the duty cycle of the DQS signal.