Memory Controller Sub-Queue Arbitration for Faster DDR Command Selection
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Solution Overview
Problem
Conventional DDR memory controllers face delays due to the arbiter taking too much time to evaluate all entries regarding priority, JEDEC timing dependency, and page state information, leading to inefficiencies in processing memory read and write commands.
Innovation Solution
Implementing a memory controller with multiple smaller command sub-queues and dedicated arbiters for each queue, allowing independent selection of memory access requests based on predetermined criteria, such as DDR timing, to increase processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single large command queue and arbiter are used, then the memory controller can handle more command entries, but the evaluation time for priority and JEDEC timing dependency increases causing delays
Solution Approach 1:
The patent divides a single large command queue into multiple smaller sub-queues (e.g., first command sub-queue, second command sub-queue, third command sub-queue, fourth command sub-queue). Each sub-queue is managed by its own dedicated arbiter, which evaluates priority and JEDEC timing dependency independently and more quickly than a single arbiter would evaluate all entries in one large queue. This segmentation reduces the evaluation time per arbiter while maintaining the total capacity to handle many command entries across all sub-queues.
2Speed
If multiple smaller command queues with dedicated arbiters are used, then the evaluation time is reduced and speed increases, but the device complexity increases
Solution Approach 1:
The patent implements multiple smaller command sub-queues (at least four sub-queues) with dedicated arbiters to reduce evaluation time and increase operating speed. Each sub-queue/arbiter pair operates independently, allowing parallel processing of memory access requests. The complexity is managed through systematic organization where each arbiter handles a specific subset of queues, and selection logic coordinates between them to determine which memory access request to execute next.
3Productivity
If a single arbiter evaluates all command queue entries, then the device structure is simpler, but the productivity and data throughput are reduced due to time-consuming evaluation
Solution Approach 1:
The patent divides the arbitration function into multiple dedicated arbiters, each responsible for evaluating priority and JEDEC timing dependency for a specific subset of command sub-queues. This segmentation enables parallel evaluation of multiple command entries simultaneously, significantly increasing data throughput and productivity compared to a single arbiter processing all entries sequentially. The increased device complexity is offset by the substantial performance gain in memory access throughput.
Data Source
AI summary
A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.