Sparse Memory Access Control for Low-Power Read and Write Bypass
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Solution Overview
Problem
Computing systems dissipate unnecessary power when accessing and storing sparse data, as reading or writing default values consumes energy despite the known outcome.
Innovation Solution
Implementing a memory system with a sparse array circuit that intercepts and halts operations for sparse data, and a data control circuit that compares data patterns to reduce power consumption by disabling unnecessary operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If memory operations are performed for all address accesses, then data retrieval and storage functionality is maintained, but power dissipation increases due to unnecessary operations on sparse data
Solution Approach 1:
The system performs preliminary comparison of the accessed address against stored sparse data addresses before executing the memory read/write operation. If the address matches a sparse data address, the operation is aborted beforehand, preventing unnecessary power consumption from completing full memory operations on known sparse data locations.
Solution Approach 2:
Instead of performing complete memory read/write operations for all addresses, the system performs only partial operations by comparing addresses first and aborting the operation entirely when sparse data is detected. This partial action approach eliminates excessive power consumption from unnecessary operations while maintaining functionality for non-sparse data.
2Loss of energy
If a sparse array circuit is added to compare addresses and generate control signals, then power dissipation is reduced by intercepting sparse data accesses, but device complexity increases
Solution Approach 1:
A sparse array circuit is introduced as an intermediary component between the memory controller and the memory array. This circuit receives address inputs, compares them against stored sparse data addresses, and generates control signals to either permit or abort memory operations. The intermediary handles the complexity of sparse data management centrally, preventing the need for complex logic distributed throughout the memory system.
Solution Approach 2:
The sparse array circuit maintains its own internal storage of sparse data addresses and autonomously performs comparisons with incoming address requests. The circuit self-manages the detection and abort logic without requiring external control, reducing the burden on the main memory controller and simplifying the overall system architecture despite adding the sparse array component.
3Loss of energy
If memory banks are disabled to reduce power consumption, then power dissipation decreases, but access time increases due to hierarchical memory architecture
Solution Approach 1:
The system performs preliminary detection of sparse data patterns before initiating memory access operations. By identifying that data at certain addresses is sparse (known default values) in advance, the system can abort access operations to disabled memory banks, avoiding the need to wait for hierarchical memory retrieval and thus reducing effective access time while maintaining power savings.
Solution Approach 2:
When sparse data is detected through address comparison, the system skips the entire memory access process for that address, rushing through the operation by immediately generating an abort signal. This skipping mechanism eliminates the time penalty of hierarchical memory access for sparse data locations while maintaining the power benefits of having memory banks disabled.
Data Source
AI summary
A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmit the sparse data pattern.