Cycle Cutting with Timing Path Analysis for Circuit Design
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Solution Overview
Problem
Conventional CAD tools are unable to process cyclical circuit designs effectively due to their inability to handle timing cycles, which are essential for high-performance, low-power circuit topologies, limiting operations such as timing optimization, element sizing, and layout.
Innovation Solution
The implementation of a cyclical timing module that analyzes and cuts timing cycles in cyclical circuit designs, preserving critical timing paths and preventing 'orphaned' elements by using a 'greatest common path' heuristic to identify false timing paths and generate cycle cut directives, allowing the designs to be represented as a directed acyclic graph for correct processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional CAD tools are used to process cyclical circuit designs, then the tools cannot handle timing cycles and perform timing optimization, but converting to acyclic design loses the high-performance, low-power benefits of cyclical topologies
Solution Approach 1:
The patent segments the cyclical circuit design into two parts: the functional cyclical logic that provides high-performance benefits, and the timing analysis representation that is converted to an acyclic directed graph. This segmentation allows CAD tools to process the design while preserving the original cyclical topology's performance characteristics through separate timing constraint specifications.
Solution Approach 2:
The patent introduces timing constraints and timing paths as an intermediary layer between the cyclical circuit design and CAD tool processing. This intermediary representation allows the tools to work with acyclic graphs while the timing constraints preserve the temporal relationships and performance characteristics of the original cyclical design.
2Ease of manufacture
If timing cycles are cut to enable CAD tool processing, then the design can be represented as a directed acyclic graph, but critical timing paths may be incorrectly removed affecting circuit functionality
Solution Approach 1:
The patent performs preliminary identification and marking of critical timing paths before the cycle cutting process. By pre-establishing which timing paths must be preserved, the subsequent acyclic graph construction and cycle cutting operations can proceed without removing these critical paths, ensuring timing constraint preservation while enabling CAD tool processing.
3Reliability
If all timing paths are preserved during cycle cutting, then timing constraints are maintained, but false timing paths increase processing complexity and reduce optimization efficiency
Solution Approach 1:
The patent applies different treatment to different timing paths based on their local characteristics. Critical timing paths that satisfy actual timing constraints are preserved with full detail, while false timing paths are identified and removed. This local quality differentiation reduces processing complexity by eliminating redundant paths while maintaining reliability for critical paths.
Data Source
AI summary
The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by traversing an adjacency list data structure, in which elements of the circuit design are represented as vertices interconnected by edges. Timing constraint paths may be distinguished from false timing paths using timing analysis, such as a greatest common path heuristic. Timing constraint paths may be marked as “constrained” to prevent these paths from being cut. With the cycles and timing constraint paths identified, cuts may be selected that cut the identified timing cycles while preserving the timing constraint paths. The cycle cuts allow the circuit design to be correctly processed within a conventional CAD tool design flow.