D2D CRC Decoder for Single-Bit Error Correction in Chiplets
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Solution Overview
Problem
Current UCIe error detection methods in chiplet communication impact bandwidth and performance due to retransmission protocols for error detection events.
Innovation Solution
Implementing a die-to-die (D2D) interface with a cyclic redundancy check (CRC) decoder that stores unique non-zero checksum error values to correct single-bit errors, reducing the need for data block retransmissions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC error detection with retransmission protocol is used, then error detection capability is improved, but chiplet communication bandwidth and performance deteriorate
Solution Approach 1:
The patent introduces an intermediary error correction code (ECC) mechanism that acts as a mediator between the data transmitter and receiver. This ECC mechanism detects and corrects single-bit errors locally at the receiver side, preventing the need for retransmission and thus maintaining communication bandwidth while improving reliability
Solution Approach 2:
The patent changes the parameter of error handling by transitioning from a retransmission-based approach to an in-situ error correction approach. By modifying the error correction code parameters and using syndrome decoding, the system can correct errors without retransmitting data, thereby resolving the contradiction between reliability and productivity
2Reliability
If retransmission protocol is implemented for error detection events, then error handling reliability is improved, but interface efficiency deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing syndrome values for all possible single-bit error patterns. When an error occurs, the receiver can immediately look up the syndrome value and correct the error without waiting for retransmission, thus improving both reliability and interface efficiency
Solution Approach 2:
The system implements self-service error correction where the receiver autonomously detects and corrects single-bit errors using the pre-stored syndrome values. This self-service capability eliminates the need for retransmission protocols, thereby improving interface efficiency while maintaining error handling reliability
Data Source
AI summary
An integrated circuit (IC) chiplet includes a die-to-die (D2D) interface with a cyclic redundancy check (CRC) decoder to process a received data block of N bits that is appended with a transmit-side CRC-16 checksum. The CRC decoder includes checksum circuitry and storage to store N unique non-zero checksum error values. Each of the N unique non-zero checksum error values represents a predicted checksum error value in the event a given bit location in the received data block of N bits is in error. Match circuitry indicates a match of a generated non-zero error checksum value to one of the N unique non-zero checksum error values in the storage. Repair circuitry corrects the given bit location corresponding to the match.